Datasheet > 8SLVD1204

8SLVD1204

更新时间： 2023-12-20 18:45:52

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
18页	796K
描述
2:4, LVDS Output Fanout Buffer, 2.5V

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8SLVD1204 数据手册

8SLVD1204

2:4, LVDS Output Fanout Buffer, 2.5V

Datasheet

Description

Features

The 8SLVD1204 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency, very

low additive phase-noise clock and data signals. The 8SLVD1204 is

characterized to operate from a 2.5V power supply. Guaranteed

output-to-output and part-to-part skew characteristics make the

8SLVD1204 ideal for those clock distribution applications demanding

well-defined performance and repeatability.

• Four low skew, low additive jitter LVDS output pairs

• Two selectable differential clock input pairs

• Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL

• Maximum input clock frequency: 2GHz

• LVCMOS/LVTTL interface levels for the control input select pin

• Output skew: 20ps (maximum)

Two selectable differential inputs and four low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs. The device is

optimized for low power consumption and low additive phase noise.

• Propagation delay: 300ps (maximum)

• Low additive phase jitter, RMS; f_REF= 156.25MHz, V_PP= 1V,

10kHz - 20MHz: 95fs (maximum)

• Full 2.5V supply voltage

• Lead-free (RoHS 6), 16-Lead VFQFPN packaging

• Supports case temperature ≤ 105°C operations

• -40°C to 85°C ambient operating temperature

Block Diagram

Pin Assignment

VDD

12 11 10

Pulldown

nQ2

VREF

PCLK0

Pullup/Pulldown

nPCLK0

PCLK0

VDD

nQ0

nQ3

GND GND

VDD

nQ1

8SLVD1204

Pulldown

PCLK1

16 lead VFQFPN

Pullup/Pulldown

nPCLK1

nQ2

3.0mm x 3.0mm x 0.9mm package body

1.7mm x 1.7mm ePad

NL Package

Top View

GND GND

VDD

nQ3

Pullup/Pulldown

SEL

GND

Reference

V_REF

Voltage

Generator

May 11, 2021 R31DS0031EU0600

12 3 4 5 6 7...18

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