Datasheet > ICS309RLF

ICS309RLF

更新时间： 2025-07-15 14:42:43

品牌	Logo	应用领域
艾迪悌 - IDT		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
10页	101K
描述
Clock Generator, 200MHz, PDSO20, 0.150 INCH, LEAD FREE, SSOP-20

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技术参数
数据手册

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ICS309RLF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	0.150 INCH, ROHS COMPLIANT, SSOP-20	针数：	20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.51
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e3	长度：	8.65 mm
湿度敏感等级：	1	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	200 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP20,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
主时钟/晶体标称频率：	50 MHz	认证状态：	Not Qualified
座面最大高度：	1.75 mm	子类别：	Clock Generators
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

ICS309RLF 数据手册

ICS309

SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH

SER PROG CLOCK SYNTHESIZER

External Components

2) The external crystal should be mounted just next to

the device with short traces. The X1 and X2 traces

should not be routed next to each other with minimum

spaces, instead they should be separated and away

from other traces.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50Ω trace (a

commonly used trace impedance), place a 33Ωresistor

in series with the clock line, as close to the clock output

pin as possible. The nominal impedance of the clock

output is 20Ω.

3) To minimize EMI, the 33Ωseries termination resistor

(if needed) should be placed close to each clock output.

STROBE Pull-up Resistor

In order for the device to start up in the default state, a

250 kOhm pull-up resistor is required.

4) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers.

Decoupling Capacitors

ICS309 Configuration Capabilities

As with any high-performance mixed-signal IC, the

ICS309 must be isolated from system power supply

noise to perform optimally.

The architecture of the ICS309 allows the user to easily

configure the device to a wide range of output

frequencies, for a given input reference frequency.

Decoupling capacitors of 0.01µF must be connected

between each VDD and the PCB ground plane.

The frequency multiplier PLL provides a high degree of

precision. The M/N values (the multiplier/divide values

available to generate the target VCO frequency) can be

set within the range of M = 1 to 2048 and N = 1 to 1024.

Crystal Load Capacitors

The device crystal connections should include pads for

small capacitors from X1 to ground and from X2 to

ground. These capacitors are used to adjust the stray

capacitance of the board to match the nominally

required crystal load capacitance. Because load

capacitance can only be increased in this trimming

process, it is important to keep stray capacitance to a

minimum by using very short PCB traces (and no vias)

been the crystal and device. Crystal capacitors must be

connected from each of the pins X1 and X2 to ground.

The ICS309 also provides separate output divide

values, from 2 through 20, to allow the two output clock

banks to support widely differing frequency values from

the same PLL.

Each output frequency can be represented as:

Output Freq. = (Ref. Freq)*(M/N)/Output Divide

IDT VersaClock Software

The value (in pF) of these crystal caps should equal (C

-6 pF)*2. In this equation, C = crystal load capacitance

IDT applies years of PLL optimization experience into a

user friendly software that accepts the user’s target

reference clock and output frequencies and generates

the lowest jitter, lowest power configuration, with only a

press of a button. The user does not need to have prior

PLL experience or determine the optimal VCO

in pF. Example: For a crystal with a 16 pF load

capacitance, each crystal capacitor would be 20 pF

[(16-6) x 2] = 20.

PCB Layout Recommendations

frequency to support multiple output frequencies.

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

VersaClock software quickly evaluates accessible VCO

frequencies with available output divide values and

provides an easy to understand, bar code rating for the

target output frequencies. The user may evaluate

output accuracy, performance trade-off scenarios in

seconds.

1) Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible. No vias should be used

between decoupling capacitor and VDD pin. The PCB

trace to VDD pin should be kept as short as possible, as

should the PCB trace to the ground via.

IDT® SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH

ICS309

REV L 091311

1 2 345 6 7...10

中文翻译

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