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IBM25PPC750GLECR5HA4T PDF预览

IBM25PPC750GLECR5HA4T

更新时间: 2023-01-03 08:46:44
品牌 Logo 应用领域
国际商业机器公司 - IBM /
页数 文件大小 规格书
76页 1031K
描述
RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA292, 21X 21 MM, 1 MM PITCH, CERAMIC, BGA-292

IBM25PPC750GLECR5HA4T 数据手册

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Datasheet  
DD 1.X  
Preliminary  
PowerPC 750GL RISC Microprocessor  
Figure 2-1. IBM PowerPC 750GL RISC Microprocessor Block Diagram ................................................. 13  
Figure 3-1. SYSCLK Input Timing Diagram .............................................................................................. 19  
Figure 3-2. Linear Sweep Modulation Profile ........................................................................................... 20  
Figure 3-3. Input Timing Definition ........................................................................................................... 22  
Figure 3-4. Input Timing Diagram ............................................................................................................. 22  
Figure 3-5. Mode Select Input Timing Diagram ........................................................................................ 23  
Figure 3-6. Output Valid Timing Definition ................................................................................................ 25  
Figure 3-7. Output Timing Diagram for IBM PowerPC 750GL RISC Microprocessor .............................. 26  
Figure 3-8. JTAG Clock Input Timing Diagram ......................................................................................... 28  
Figure 3-9. TRST Timing Diagram ........................................................................................................... 28  
Figure 3-10. Boundary-Scan Timing Diagram ............................................................................................ 28  
Figure 3-11. Test Access Port Timing Diagram .......................................................................................... 29  
Figure 4-1. Mechanical Dimensions, Standard (Leaded) Package .......................................................... 31  
Figure 4-2. Mechanical Dimensions, ROHS-Compatible Package .......................................................... 33  
Figure 4-3. Module Substrate Decoupling Voltage Assignments ............................................................. 35  
Figure 4-4. PowerPC 750GL Microprocessor Ball Placement .................................................................. 36  
Figure 5-1. Single PLL Power Supply Filter Circuit with A1VDD Pin and A2VDD Pin Tied to GND ......... 51  
Figure 5-2. PLL Power Supply Filter Circuit with Two AVDD Pins and One Ferrite Bead ........................ 51  
Figure 5-3. Dual PLL Power Supply Filter Circuits ................................................................................... 53  
Figure 5-4. Orientation and Layout of the 750GL Decoupling Capacitors ................................................ 56  
Figure 5-5. Driver Impedance Measurement ............................................................................................ 57  
Figure 5-6. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector ........................ 62  
Figure 5-7. Package Exploded Cross-Sectional View with Several Heat-Sink Options ........................... 63  
Figure 5-8. C4 Package with Heat Sink Mounted to a Printed-Circuit Board ........................................... 66  
Figure 5-9. Thermal Performance of Select Thermal Interface Material .................................................. 67  
Figure 5-10. Example of a Pin-Fin Heat-Sink-to-Ambient Thermal Resistance versus Airflow Velocity .... 69  
750GL_dsLOF.fm.1.2  
March 13, 2006  
Page 7 of 74  

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