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IBM0436A41QLAB-3N PDF预览

IBM0436A41QLAB-3N

更新时间: 2024-01-14 01:34:19
品牌 Logo 应用领域
国际商业机器公司 - IBM 静态存储器内存集成电路
页数 文件大小 规格书
26页 141K
描述
Standard SRAM, 128KX36, 1.8ns, CMOS, PBGA119, BGA-119

IBM0436A41QLAB-3N 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Contact Manufacturer零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.66
Is Samacsys:N最长访问时间:1.8 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:4718592 bit内存集成电路类型:STANDARD SRAM
内存宽度:36功能数量:1
端子数量:119字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.5,3.3 V
认证状态:Not Qualified座面最大高度:2.679 mm
最大待机电流:0.1 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.435 mA
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

IBM0436A41QLAB-3N 数据手册

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IBM0418A81QLAB IBM0436A81QLAB  
IBM0418A41QLAB IBM0436A41QLAB  
8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM  
Features  
• 8Mb: 256K x 36 or 512K x 18 organizations  
4Mb: 128K x 36 or 256K x 18 organizations  
• Registered Outputs  
• Common I/O  
• 0.25 Micron CMOS technology  
• Asynchronous Output Enable  
• Synchronous Power Down Input  
• Synchronous Pipeline Mode of Operation with  
Self-Timed Late Write  
• Boundary Scan using limited set of JTAG  
1149.1 functions  
• Single Differential Extended HSTL Clock  
• +3.3V Power Supply, Ground, 1.5V V  
, and  
DDQ  
• Byte Write Capability and Global Write Enable  
0.75V V  
REF  
• 7 x 17 Bump Ball Grid Array Package with  
SRAM JEDEC Standard Pinout and Boundary  
SCAN Order  
• HSTL Input and Output levels  
• Registered Addresses, Write Enables, Synchro-  
nous Select, and Data Ins  
Description  
The 4Mb and 8Mb SRAMs—IBM0436A41QLAB,  
IBM0418A41QLAB, IBM0418A81QLAB, and  
IBM0436A81QLAB—are Synchronous Pipeline  
Mode, high-performance CMOS Static Random  
Access Memories that are versatile, have wide I/O,  
and can achieve 3.0ns cycle times. Differential K  
clocks are used to initiate the read/write operation  
and all internal operations are self-timed. At the ris-  
ing edge of the K clock, all Addresses, Write-  
Enables, Sync Select, and Data Ins are registered  
internally. Data Outs are updated from output regis-  
ters off the next rising edge of the K clock. An inter-  
nal Write buffer allows write data to follow one cycle  
after addresses and controls. The chip is operated  
with a single +3.3V power supply and is compatible  
with HSTL I/O interfaces.  
crrh3316.08  
12/00  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
Page 1 of 26  
 

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