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HYB18RL28836AC-3.3 PDF预览

HYB18RL28836AC-3.3

更新时间: 2024-02-05 01:32:12
品牌 Logo 应用领域
英飞凌 - INFINEON 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
50页 736K
描述
DDR DRAM, 8MX36, CMOS, PBGA144, PLASTIC, TFBGA-144

HYB18RL28836AC-3.3 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TBGA,针数:144
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.84
访问模式:MULTI BANK PAGE BURST其他特性:AUTO REFRESH
JESD-30 代码:R-PBGA-B144长度:18.5 mm
内存密度:301989888 bit内存集成电路类型:DDR DRAM
内存宽度:36功能数量:1
端口数量:1端子数量:144
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS组织:8MX36
封装主体材料:PLASTIC/EPOXY封装代码:TBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:11 mmBase Number Matches:1

HYB18RL28836AC-3.3 数据手册

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HYB18RL28818/36AC  
288 Mbit DDR Reduced Latency DRAM  
Edition July 2003  
This edition was realized using the software system FrameMaker .  
Published by Infineon Technologies,  
Marketing-Kommunikation,  
Balanstraße 73,  
81541 München  
© Infineon Technologies 4/01/03.  
All Rights Reserved.  
Attention please!  
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits imple-  
mented within components or assemblies.  
The information describes the type of component and shall not be considered as assured characteristics.  
Terms of delivery and rights to change design reserved.  
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies  
and Representatives worldwide (see address list).  
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest In-  
fineon Technologies Office.  
Infineon Technologies is an approved CECC manufacturer.  
Packing  
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing  
material back, if it is sorted. You must bear the costs of transport.  
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.  
Components used in life-support devices or systems must be expressly authorized for such purpose!  
1
2
Critical components of Infineon Technologies, may only be used in life-support devices or systems with the express written approval of Infineon Tech-  
nologies.  
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-  
support device or system, or to affect its safety or effectiveness of that device or system.  
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they  
fail, it is reasonable to assume that the health of the user may be endangered.  
HYB18RL28818/36AC  
Revision History: Current Version 1.60  
Subjects (major changes since last revision)  
Previous Version: 1.51  
frontpage  
frontpage  
fixed part number HYB18RL28809AC -> HYB18RL28890AC  
removed confidential  
all  
all  
48  
48  
x36 configuration table, swapped pins F12 and E12  
11  
11  
Ball Description table - ZQ - added ‘...connected to GND, then minimum DQ output impedance is set.’  
Re-numbered scan registers order, starting with 0 to 112  
Removed the word “Isolated” from the Vddq power supply description in table 18  
Added note 7 for Vtt. A power supply should be used for Vtt generation, not a voltage divider.  
Changed the value of tMRSC from 6 to 12 clocks  
46,47,48  
52  
46,47,48  
52  
52  
52  
19  
19  
49  
49  
Figure 40, Tap Block Diagram. Added numbering to scan chain order.  
Added tCKvar, added notes 4 and 5. (jitter parameter)  
16  
16  
11  
11  
Add to ZQ, QVLD, DQ, QK that the output impedance of QVLD, DQ, and QKx is controlled via ZQ  
Comment that states each RD/WR is a row access, wait tRC before next RD/WR to same bank.  
added: (8k refresh per bank, 64k total refresh cycles each 32ms)  
Idle means all commands complete, no more burst or refresh occuring  
Added power estimates.  
20,21,25  
32  
20,21,25  
32  
19  
19  
54  
54  
5,52  
all  
5,52  
all  
Remove 1.5v VDDQ option  
Removed x9 option  
Version 1.60  
Page 2  
Infineon Technologies  
This specification is preliminary and subject to change without notice  

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