HYB18RL28818/36AC
288 Mbit DDR Reduced Latency DRAM
Edition July 2003
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HYB18RL28818/36AC
Revision History: Current Version 1.60
Subjects (major changes since last revision)
Previous Version: 1.51
frontpage
frontpage
fixed part number HYB18RL28809AC -> HYB18RL28890AC
removed confidential
all
all
48
48
x36 configuration table, swapped pins F12 and E12
11
11
Ball Description table - ZQ - added ‘...connected to GND, then minimum DQ output impedance is set.’
Re-numbered scan registers order, starting with 0 to 112
Removed the word “Isolated” from the Vddq power supply description in table 18
Added note 7 for Vtt. A power supply should be used for Vtt generation, not a voltage divider.
Changed the value of tMRSC from 6 to 12 clocks
46,47,48
52
46,47,48
52
52
52
19
19
49
49
Figure 40, Tap Block Diagram. Added numbering to scan chain order.
Added tCKvar, added notes 4 and 5. (jitter parameter)
16
16
11
11
Add to ZQ, QVLD, DQ, QK that the output impedance of QVLD, DQ, and QKx is controlled via ZQ
Comment that states each RD/WR is a row access, wait tRC before next RD/WR to same bank.
added: (8k refresh per bank, 64k total refresh cycles each 32ms)
Idle means all commands complete, no more burst or refresh occuring
Added power estimates.
20,21,25
32
20,21,25
32
19
19
54
54
5,52
all
5,52
all
Remove 1.5v VDDQ option
Removed x9 option
Version 1.60
Page 2
Infineon Technologies
This specification is preliminary and subject to change without notice