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HY5DS113222FM-4 PDF预览

HY5DS113222FM-4

更新时间: 2024-01-16 00:22:59
品牌 Logo 应用领域
海力士 - HYNIX 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
30页 432K
描述
512M(16Mx32) GDDR SDRAM

HY5DS113222FM-4 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA, BGA144,12X12,32
针数:144Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.92Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:0.6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):250 MHz
I/O 类型:COMMON交错的突发长度:2,4,8
JESD-30 代码:S-PBGA-B144长度:12 mm
内存密度:536870912 bit内存集成电路类型:DDR DRAM
内存宽度:32功能数量:1
端口数量:1端子数量:144
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA144,12X12,32
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not Qualified刷新周期:4096
座面最大高度:1.3 mm自我刷新:YES
连续突发长度:2,4,8最大待机电流:0.05 A
子类别:DRAMs最大压摆率:0.62 mA
最大供电电压 (Vsup):2.1 V最小供电电压 (Vsup):1.75 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:12 mmBase Number Matches:1

HY5DS113222FM-4 数据手册

 浏览型号HY5DS113222FM-4的Datasheet PDF文件第1页浏览型号HY5DS113222FM-4的Datasheet PDF文件第2页浏览型号HY5DS113222FM-4的Datasheet PDF文件第4页浏览型号HY5DS113222FM-4的Datasheet PDF文件第5页浏览型号HY5DS113222FM-4的Datasheet PDF文件第6页浏览型号HY5DS113222FM-4的Datasheet PDF文件第7页 
HY5DS113222FM(P)  
Preliminary  
DESCRIPTION  
The Hynix HY5DS113222FM(P) is a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM which consists  
of two 256Mbit(x32) - Multi-chip-, ideally suited for the point-to-point applications which requires high bandwidth.  
The Hynix 16Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the  
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,  
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-  
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible  
with SSTL_2.  
FEATURES  
The Hynix HY5DS113222FM(P) guarantee until  
166MHz speed at DLL_off condition  
Data(DQ) and Write masks(DM) latched on the both  
rising and falling edges of the data strobe  
1.8V VDD and VDDQ wide range max power supply  
All addresses and control inputs except Data, Data  
strobes and Data masks latched on the rising edges  
of the clock  
All inputs and outputs are compatible with SSTL_2  
interface  
Write mask byte controls by DM (DM0 ~ DM3)  
Programmable /CAS Latency 5, 4 supported  
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch  
Fully differential clock inputs (CK, /CK) operation  
Programmable Burst Length 2 / 4 / 8 with both  
sequential and interleave mode  
The signals of Chip select control the each chip with  
CS0 and CS1, individually.  
Internal 4 bank operations with single pulsed /RAS  
tRAS Lock-Out function supported  
Double data rate interface  
Source synchronous - data transaction aligned to  
bidirectional data strobe (DQS0 ~ DQS3)  
Auto refresh and self refresh supported  
4096 refresh cycles / 32ms  
Data outputs on DQS edges when read (edged DQ)  
Data inputs on DQS centers when write (centered  
DQ)  
(Both chips do refresh operation, simultaneously)  
Half strength and Matched Impedance driver option  
controlled by EMRS  
ORDERING INFORMATION  
Power  
Supply  
Clock  
Frequency  
Part No.  
Max Data Rate  
interface  
Package  
HY5DS113222FM(P)-28  
HY5DS113222FM(P)-33  
HY5DS113222FM(P)-36  
HY5DS113222FM(P)-4  
350MHz  
300MHz  
275MHz  
250MHz  
700Mbps/pin  
600Mbps/pin  
550Mbps/pin  
500Mbps/pin  
12mmx12mm  
144Ball FBGA  
VDD, VDDQ=  
SSTL_2  
1.8V  
Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.  
We'll add "P" character after "FM" for lead free product. For example, the part number of 300MHz Lead free  
product is HY5DS113222FM(P) - 33.  
Rev. 0.1 / Oct. 2004  
3

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