HT45R22E
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
tSYS
tSYS
For HXT/LXT
1024
2
¾
¾
¾
¾
tSST
System Start-up time Period
¾
For ERC/IRC
(By configuration option)
tINT
Interrupt Pulse Width
1
¾
¾
¾
¾
¾
¾
¾
1
¾
2
ms
ms
ms
tLVR
Low Voltage Width to Reset
0.25
¾
RESTD Reset Delay Time
100
¾
Note: 1. tSYS=1/fSYS
2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
EEPROM - A.C. Characteristics
Standard Mode*
VCC=3V±10%
Symbol
Parameter
Clock Frequency
Remark
Unit
Min.
¾
Max.
100
¾
Min.
¾
Max.
400
¾
fSK
tHIGH
tLOW
tr
kHz
ns
¾
¾
¾
Clock High Time
4000
4700
¾
600
1200
¾
Clock Low Time
ns
¾
¾
SDA and SCL Rise Time
SDA and SCL Fall Time
Note
Note
1000
300
300
300
ns
tf
ns
¾
¾
After this period the first
clock pulse is generated
tHD:STA
START Condition Hold Time
START Condition Setup Time
4000
4000
600
600
ns
ns
¾
¾
¾
¾
Only relevant for repeated
START condition
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tAA
Data Input Hold Time
0
0
ns
ns
ns
ns
¾
¾
¾
¾
¾
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
200
4000
¾
100
600
¾
¾
¾
¾
¾
3500
900
¾
Time in which the bus
tBUF
Bus Free Time
must be free before a new 4700
transmission can start
1200
ns
¾
¾
Input Filter Time Constant
(SDA and SCL Pins)
tSP
Noise suppression time
100
5
50
5
ns
¾
¾
¾
¾
tWR
Write Cycle Time
ms
¾
Notes: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 3.6V
For relative timing, refer to timing diagrams
Rev. 1.00
7
March 17, 2010