HT45F5N/HT45FH5N
Power Bank ASSP Flash MCU
RAM Data Memory......................................................................................... 32
Stꢂuctuꢂe ............................................................................................................................... 3ꢅ
Data Meꢀoꢂy Addꢂessing...................................................................................................... 33
Geneꢂal Puꢂpose Data Meꢀoꢂy ............................................................................................ 33
Special Puꢂpose Data Meꢀoꢂy ............................................................................................. 33
Special Function Register Description........................................................ 35
Indiꢂect Addꢂessing Registeꢂs – IAR0ꢄ IAR1ꢄ IARꢅ ............................................................... 35
Meꢀoꢂy Pointeꢂs – MP0ꢄ MP1Lꢄ MP1Hꢄ MPꢅLꢄ MPꢅH......................................................... 35
Accuꢀulatoꢂ – ACC .............................................................................................................. 37
Pꢂogꢂaꢀ Counteꢂ Low Registeꢂ – PCL ................................................................................. 37
Look-up Taꢁle Registeꢂs – TBLPꢄ TBHPꢄ TBLH .................................................................... 37
Status Registeꢂ – STATUS ................................................................................................... 37
EEPROM Data Memory.................................................................................. 39
EEPROM Data Meꢀoꢂy Stꢂuctuꢂe ........................................................................................ 39
EEPROM Registeꢂs .............................................................................................................. 39
Reading Data fꢂoꢀ the EEPROM ......................................................................................... 41
Wꢂiting Data to the EEPROM................................................................................................ 41
Wꢂite Pꢂotection..................................................................................................................... 41
EEPROM Inteꢂꢂupt ................................................................................................................ 41
Pꢂogꢂaꢀꢀing Consideꢂations................................................................................................ 4ꢅ
Oscillators ...................................................................................................... 43
Oscillatoꢂ Oveꢂview ............................................................................................................... 43
System Clock Configurations................................................................................................ 43
Inteꢂnal RC Oscillatoꢂ – HIRC ............................................................................................... 44
Inteꢂnal 3ꢅkHz Oscillatoꢂ – LIRC .......................................................................................... 44
Operating Modes and System Clocks ......................................................... 44
Systeꢀ Clocks ...................................................................................................................... 44
Systeꢀ Opeꢂation Modes ..................................................................................................... 45
Contꢂol Registeꢂ .................................................................................................................... 4ꢆ
Opeꢂating Mode Switching ................................................................................................... 4ꢃ
Standꢁy Cuꢂꢂent Consideꢂations .......................................................................................... 51
Wake-up ............................................................................................................................... 5ꢅ
Watchdog Timer............................................................................................. 53
Watchdog Tiꢀeꢂ Clock Souꢂce.............................................................................................. 53
Watchdog Tiꢀeꢂ Contꢂol Registeꢂ......................................................................................... 53
Watchdog Tiꢀeꢂ Opeꢂation ................................................................................................... 54
Reset and Initialisation ................................................................................. 55
Reset Functions .................................................................................................................... 55
Reset Initial Conditions ........................................................................................................ 57
Input / Output Ports ...................................................................................... 62
Pull-high Resistoꢂs ................................................................................................................ ꢆꢅ
Poꢂt A Wake-up ..................................................................................................................... ꢆ3
I/O Poꢂt Contꢂol Registeꢂs..................................................................................................... ꢆ4
Slew Rate Contꢂol ................................................................................................................. ꢆ5
Rev. 1.00
3
�oveꢀꢁeꢂ 1ꢃꢄ ꢅ01ꢆ
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