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HT32F1655 PDF预览

HT32F1655

更新时间: 2022-02-26 12:43:34
品牌 Logo 应用领域
台湾合泰/盛群 - HOLTEK 微控制器静态存储器
页数 文件大小 规格书
48页 1344K
描述
32-bit ARM Cortex -M3 Microcontroller,up to 256KB Flash and 32KB SRAM with 1 MSPS

HT32F1655 数据手册

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3ꢃ-bit ARM® Cortex™-M3 MCU  
HT3ꢃF1656/HT3ꢃF1655  
Features  
2
Core  
32-bit ARM® Cortex™-M3 processor core  
Up to 72 MHz operating frequency  
1.25 DMIPS/MHz (Dhrystone 2.1)  
Single-cycle multiplication and hardware division  
Integrated Nested Vectored Interrupt Controller (NVIC)  
24-bit SysTick timer  
The Cortex™-M3 processor is a general-purpose 32-bit processor core especially suitable for  
products requiring high performance and low power consumption microcontrollers. It offers many  
special features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond  
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3  
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction  
sets.  
On-chip Memory  
Up to 256 KB on-chip Flash memory for instruction/data and option storage  
32 KB on-chip SRAM  
Supports multiple boot modes  
The ARM® Cortex™-M3 processor is structured using Harvard architecture which uses a separate  
bus structure to fetch instructions and load/store data. The instruction code and data are both  
located in the same memory address space but in different address ranges. The maximum address  
range of the Cortex™-M3 is 4 GB due to its 32-bit bus address width. Additionally, a pre-defined  
memory map is provided by the Cortex™-M3 processor to reduce the software complexity of  
repeated implementation for different device vendors. However, some regions are used by the  
ARM® Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference  
Manual for more information. Figure 2 shows the memory map of the HT32F1656/55 series of  
devices, including Code, SRAM, peripheral, and other pre-defined regions.  
Flash Memory Controller  
Flash accelerator for maximum efficiency  
32-bit word programming with In System Programming Interface (ISP) and In Application  
Programming (IAP)  
Flash protection capability to prevent illegal access  
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer  
for the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower  
than the CPU, a wide access interface with a pre-fetch buffer and cache are provided for the Flash  
Memory in order to reduce the CPU waiting time which will cause CPU instruction execution  
delays. Flash Memory word program/page erase functions are also provided.  
Rev. 1.00  
7 of ꢄ8  
�ꢀꢁꢂ ꢃꢄꢅ ꢃ01ꢄ  

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