Datasheet > HMS25632M8B-17

HMS25632M8B-17

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
HANBIT		静态存储器
页数	文件大小	规格书
9页	233K
描述
SRAM MODULE 1Mbyte (256K x 32-Bit) , 72-Pin

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数据手册

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HMS25632M8B-17 数据手册

HANBit

HMS25632M8B/Z8B

(/OE Low Fixed )

TIMING WAVEFORM OF WRITE CYCLE

t_WC

Address

t_AW

t_WR(5)

t_CW(3)

/CE

t_AS(4)

t_OH

t_WP(2)

/WE

t_DW

t_DH

High-Z

Data In

t_WHZ(6,7)

t_OW

(10)

(9)

High-Z(8)

Data Out

(Write Cycle)

Notes

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among

/CE going low and /WE going low : A write ends at the earliest transition among /CE going high and /WE going high.

t_WPis measured from the beginning of write to the end of write.

3. t_CWis measured from the later of /CE going low to the end of write.

4. t_ASis measured from the address valid to the beginning of write.

5. t_WRis measured from the end of write to the address change. t_WRapplied in case a write ends as /CE, or /WE going high.

6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of

opposite phase of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.

9. D_OUTis the read data of the new address.

10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

FUNCTIONAL DESCRIPTION

/CE

/WE

/OE

MODE

Not Select

Output Disable

Read

I/O PIN

High-Z

D_OUT

SUPPLY CURRENT

l _SB, l _SB1

l_CC

Write

D_IN

l_CC

Note: X means Don't Care

HANBit Electronics Co.,Ltd.

1...4 5 678 9

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