Datasheet > HMS12832M4

HMS12832M4

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
HANBIT		静态存储器
页数	文件大小	规格书
9页	196K
描述
SRAM MODULE 512KByte (128K x 32-Bit)

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数据手册

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HMS12832M4 数据手册

HANBit

HMS12832M4

( /CE Controlled )

t_RC

TIMING WAVEFORM OF READ CYCLE

Address

/CE

t_HZ(3,4,5)

t_AA

t_CO

t_LZ(4,5)

t_OHZ

t_OE

/OE

t_OH

t_OLZ

High-Z

Data Out

Data Valid

t_PD

t_PU

50%

l_CC

l_SB

Vcc Supply

Current

50%

(Read Cycle)

Notes

1. /WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to first transition address.

3. t_HZand t_OHZare defined as the time at which the outputs achieve the open circuit condition and are not referenced to V_OH

or V_OLlevels.

4. At any given temperature and voltage condition, t_HZ(max.) is less than t_LZ(min.) both for a given device and from device

to device.

5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with /CE = V_IL.

7. Address valid prior to coincident with /CE transition low.

(/OE=Clock )

TIMING WAVEFORM OF WRITE CYCLE

t_WC

Address

/OE

t_AW

t_WR(5)

t_CW(3)

/CE

t_AS(4)

t_WP(2)

/WE

t_DW

t_DH

High-Z

Data In

Data Valid

t_OHZ(6)

t_OW

Data Out

High-Z

HANBit Electronics Co.,Ltd.

1...3 4 567 8 9

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