HANBit
HMF1M32F2VA
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
PARAMETER
UNIT
COMMENTS
MIN.
TYP.
0.7
25
MAX.
Sector Erase Time
Chip Erase Time
-
15
sec
sec
ms
Excludes 00H programming
prior to erasure
Byte Programming Time
Chip Programming Time
-
-
9
300
54
Excludes system-level
overhead
18
sec
TSOP CAPACITANCE
PARAMETER
SYMBOL
PARAMETER
DESCRIPTION
TEST SETUP
MIN
MAX
UNIT
CIN
COUT
CIN2
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
6
7.5
12
9
pF
pF
pF
Output Capacitance
8.5
7.5
Control Pin Capacitance
: Test conditions TA = 25o C, f=1.0 MHz.
Notes
TEST SPECIFICATIONS
TEST CONDITION
70R, 80
90, 120
UNIT
Output load
1TTL gate
Output load capacitance,CL (Including jig capacitance)
Input rise and full times
30
100
pF
ns
V
5
0.0-3.0
1.5
Input pulse levels
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
AC CHARACTERISTICS
Read Only Operations Characteristics
u
PARAMETER
SYMBOLS
Speed Options
DESCRIPTION
TEST SETUP
UNIT
-70R
-80
JEDEC STANDARD
-90
-120
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
tOE
tDF
Read Cycle Time
Min
70
70
80
80
80
30
25
25
90
90
90
35
30
30
120
120
120
35
ns
ns
ns
ns
ns
ns
ns
/CE = VIL
/OE = VIL
Max
Address to Output Delay
Chip Enable to Output Delay
Chip Enable to Output Delay
Chip Enable to Output High-Z
/OE = VIL
Max
Max
Max
Max
Min
70
30
25
25
30
tDF
Output Enable to Output High-Z
Output Hold Time From Addresses,
/CE or /OE, Whichever Occurs First
30
0
tQH
4
URL: www.hbe.co.kr
REV.02(August,2002)
HANBit Electronics Co., Ltd.