HANBit
HMF1M32F2VA
Flash-ROM Module 4MByte (1Mx32Bit), 80Pin-SMM, 3.3V Design
HMF1M32F2VA
Part No.
GENERAL DESCRIPTION
The HMF1M32F2VA is a high-speed flash read only memory (FROM) module containing 1,048,576 words organized in a
x32bit configuration. The module consists of two 1M x 16 FROM mounted on a 80-pin stackable type, double - sided, FR4-
printed circuit board.
Commands are written to the command register using standard microprocessor write timings.
Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the
device is similar to reading from 12.0V flash or EPROM devices.
Output enable (/OE) and write enable (/WE) can set the memory input and output. The host system can detect a program or
erase operation is complete by observing the Ready Pin, or reading the DQ7(Data # Polling) and DQ6(Toggle) status bits.
When FROM module is disable condition the module is becoming power standby mode, system designer can g et low-power
design. All module components may be powered from a single + 3.0V DC power supply and all inputs and outputs are LVTTL-
compatible.
FEATURES
PIN ASSIGNMENT
P1
PIN Symbol PIN Symbol
P2
w Part Identification
PIN
1
Symbol
Vcc
PIN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Symbol
Vcc
- HMF1M32F2VA : Socket 5mm
w Access time: 70, 80, 90, 120ns
w High-density 4MByte design
w High-reliability, low-power design
1
2
Vcc
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Vcc
DQ16
DQ24
DQ17
DQ25
DQ18
Vss
2
DQ15
DQ7
DQ14
DQ6
DQ13
Vss
NC
3
NC
3
NC
4
NC
4
/BYTE
/OE
/CE
w Single + 3.0V 0.5V power supply
±
5
NC
5
w All in/outputs are LVTTL-compatible
w FR4-PCB design
6
/RY_BY
Vss
6
7
7
Vss
w 80-pin Designed by
8
/RESET
/WE
A10
A21
A20
A19
Vss
DQ26
DQ19
DQ27
DQ20
DQ28
DQ21
Vss
8
DQ5
DQ12
DQ4
DQ11
DQ3
DQ10
Vss
A13
A29
A11
A12
A22
A23
Vss
40-pin Fine Pitch Connector (x 2EA)
w Minimum 1,000,000 write/erase cycle
w Sector erases architecture
9
9
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
OPTIONS
MARKING
w Timing
70ns access
80ns access
90ns access
120ns access
w Packages
80-pin SMM
-70
A18
A17
A16
A15
A14
Vcc
DQ29
DQ22
DQ30
DQ23
DQ31
Vcc
DQ2
DQ9
DQ1
DQ8
DQ0
Vcc
A24
A25
A26
A27
A28
Vcc
-80
-90
-120
F
4 cf : Address & Data Bus is organized for LG Specification.
( A10 & DQ0 are MSB, A29 & DQ31 are LSB )
1
URL: www.hbe.co.kr
REV.02(August,2002)
HANBit Electronics Co., Ltd.