Datasheet > HMC424A-SX

HMC424A-SX

更新时间： 2022-06-24 15:43:07

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
11页	285K
描述
0.1 GHz to 13.0 GHz,0.5 dB LSB, 6-Bit, GaAs Digital Attenuator

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HMC424A-SX 数据手册

Data Sheet

HMC424ACHIPS

THEORY OF OPERATION

The HMC424ACHIPS incorporates a 6-bit attenuator die that

offers an attenuation range of 31.5 dB in 0.5 dB steps. The

attenuation state is changed by the parallel control voltage

inputs (V1 to V6) directly (see Table 5).

RF INPUT AND OUTPUT

The attenuator in the HMC424ACHIPS is bidirectional. The

RF1 and RF2 pins are interchangeable as the RF input and

output ports. The attenuator is internally matched to 50 Ω at

both the input and the output. Therefore, no external matching

components are required.

The HMC424ACHIPS allows the user to program the

attenuation state via six parallel control inputs toggled between

0 V and V_EE. When interfacing with a TTL/CMOS interface, an

external level shifter is required. An example simple driver

using standard logic ICs provides fast switching while using

minimum dc current. The series resistance is recommended to

suppress unwanted RF signals at the input of the V1 to V6

control lines.

The RF input and output pins of the HMC424ACHIPS are

internally dc biased to 0 V. T herefore, they require external dc

blocking capacitors if the RF line potential is not equal to 0 V.

Select the value of these dc blocking capacitors based on the

minimum operating frequency. Use larger value capacitors to

extend the operation to lower frequencies.

POWER SUPPLY

= 5.1V

= 50µA

COMPENSATED

DEVICES

The HMC424ACHIPS requires a single dc voltage applied to

the VEE pin. The ideal power-up sequence is as follows:

CD4689

TO GaAs IC

TTL

CMOS

100Ω

74HCT04 (TTL)

ATTENUATOR

CONTROL INPUTS

V1 TO V6

1. Connect the ground reference.

GND

10kΩ

2. Apply a supply voltage to the VEE pin.

3. Power up the digital control inputs. The relative order of

the digital control inputs is not important.

4. Apply an RF input signal to RF1.

OR 74HC04 (CMOS)

–5V dc

NOTE

CD4689 IS A ZENER DIODE. V IS THE ZENER VOLTAGE, AND I

IS THE ZENER TEST CURRENT.

The power-down sequence is the reverse of the power-up

sequence.

Figure 23. Suggested Driver Circuit

Table 5. V1 to V6 Truth Table

Control Voltage Input

V1 (16 dB)

Low

V2 (8 dB)

Low

V3 (4 dB)

Low

V4 (2 dB)

Low

V5 (1 dB)

Low

V6 (0.5 dB)

Low

Attenuation State, RF1 to RF2

Reference insertion loss

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

High

Low

0.5 dB

1 dB

2 dB

4 dB

8 dB

Low

High

Low

High

Low

High

Low

High

16 dB

31.5 dB

¹Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected.

Rev. B | Page 9 of 11

1...6 7 8910 11

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