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HIP6302

更新时间： 2024-02-17 18:11:33
品牌 Logo 应用领域
英特矽尔 - INTERSIL 调节器微处理器多相元件控制器
页数 文件大小 规格书
17页 186K
描述
Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller

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中文翻译

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HIP6302 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOIC-16
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.19Is Samacsys：N
模拟集成电路 - 其他类型：SWITCHING CONTROLLER控制模式：CURRENT/VOLTAGE-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：5.25 V
最小输入电压：4.75 V标称输入电压：5 V
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：9.9 mm湿度敏感等级：3
功能数量：1端子数量：16
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：PHASE-SHIFT最大切换频率：1500 kHz
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mmBase Number Matches：1

HIP6302 数据手册

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HIP6302  
than the average current, the signal applied via the summing  
three state condition that makes these outputs essentially  
open. This state results in no gate drive to the output  
MOSFETS.  
Correction circuit to the Comparator, reduces the output  
pulse width of the Comparator to compensate for the  
detected “above average” current in that channel.  
Once the V  
voltage reaches 4.375V (+125mV), a voltage  
CC  
level to insure proper internal function, the PWM outputs are  
enabled and the Soft-Start sequence is initiated. If for any  
Droop Compensation  
In addition to control of each power channel’s output current,  
the average channel current is also used to provide CORE  
voltage “droop” compensation. Average full channel current  
reason, the V  
voltage drops below 3.875V (+125mV). the  
CC  
POR circuit shuts the converter down and again three states  
the PWM outputs.  
is defined as 50µA. By selecting an input resistor, R , the  
IN  
amount of voltage droop required at full load current can be  
programmed. The average current driven into the FB pin  
Soft-Start  
After the POR function is completed with V  
CC  
reaching  
results in a voltage increase across resistor R that is in the  
IN  
4.375V, the Soft-Start sequence is initiated. Soft-Start, by its  
slow rise in CORE voltage from zero, avoids an over-current  
condition by slowly charging the discharged output  
capacitors. This voltage rise is initiated by an internal DAC  
that slowly raises the reference voltage to the error amplifier  
input. The voltage rise is controlled by the oscillator  
frequency and the DAC within the HIP6302, therefore, the  
output voltage is effectively regulated as it rises to the final  
programmed CORE voltage value.  
direction to make the Error Amplifier “see” a higher voltage  
at the inverting input, resulting in the Error Amplifier  
adjusting the output voltage lower. The voltage developed  
across R is equal to the “droop” voltage. See the “Current  
IN  
Sensing and Balancing” section for more details.  
Applications and Convertor Start-Up  
Each PWM power channel’s current is regulated. This  
enables the PWM channels to accurately share the load  
current for enhanced reliability. The HIP6601, HIP6602 or  
HIP6603 MOSFET driver interfaces with the HIP6302. For  
more information, see the HIP6601, HIP6602 or HIP6603  
data sheets.  
For the first 32 PWM switching cycles, the DAC output  
remains inhibited and the PWM outputs remain three stated.  
From the 33rd cycle and for another, approximately 150  
cycles the PWM output remains low, clamping the lower  
output MOSFETs to ground, see Figure 3. The time  
variability is due to the Error Amplifier, Sawtooth Generator  
and Comparators moving into their active regions. After this  
short interval, the PWM outputs are enabled and increment  
the PWM pulse width from zero duty cycle to operational  
pulse width, thus allowing the output voltage to slowly reach  
the CORE voltage. The CORE voltage will reach its  
programmed value before the 2048 cycles, but the PGOOD  
output will not be initiated until the 2048th PWM switching  
cycle.  
o
The HIP6302 controls the two PWM power channels 180  
out of phase. Figure 2 shows the out of phase relationship  
between the two PWM channels.  
PWM 1  
PWM 2  
The Soft-Start time or delay time, DT = 2048/F . For an  
SW  
oscillator frequency, F , of 200kHz, the first 32 cycles or  
SW  
FIGURE 2. TWO PHASE PWM OUTPUT AT 500kHz  
160µs, the PWM outputs are held in a three state level as  
explained above. After this period and a short interval  
described above, the PWM outputs are initiated and the  
voltage rises in 10.08ms, for a total delay time DT of  
10.24ms.  
Power supply ripple frequency is determined by the channel  
frequency, F , multiplied by the number of active channels.  
SW  
For example, if the channel frequency is set to 250kHz, the  
ripple frequency is 500kHz.  
Figure 3 shows the start-up sequence as initiated by a fast  
The IC monitors and precisely regulates the CORE voltage  
of a microprocessor. After initial start-up, the controller also  
provides protection for the load and the power supply. The  
following section discusses these features.  
rising 5V supply, V  
applied to the HIP6302. Note the  
CC,  
short rise to the three state level in PWM 1 output during first  
32 PWM cycles.  
Initialization  
The HIP6302 usually operates from an ATX power supply.  
Many functions are initiated by the rising supply voltage to  
the V  
pin of the HIP6302. Oscillator, Sawtooth Generator,  
CC  
Soft-Start and other functions are initialized during this  
interval. These circuits are controlled by POR, Power-On  
Reset. During this interval, the PWM outputs are driven to a  
8
1...567891011...17

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