HIP1011D, HIP1011E
®
Data Sheet
November 18, 2004
FN4725.5
Dual Slot PCI Hot Plug Controllers
Features
• Independent Power Control of 2 PCI Slots
• Turn-Off Delay Time Adjustability
• Internal MOSFET Switches for +12V and -12V Outputs
• µP Interface for On/Off Control and Fault Reporting
• Adjustable Overcurrent Protection for All Eight Supplies
• Provides Fault Isolation
The HIP1011D, HIP1011E are the first ICs available for
independent control of two PCI Hot-Plug slots. The
HIP1011D has all the features and functionality of two single
PCI Hot-Plug slot controllers such as the HIP1011A but in
the same foot print area. Like the single slot HIP1011B, the
HIP1011E does not monitor output voltage nor respond to
undervoltage conditions.
The HIP1011D, HIP1011E are designed to be physically
placed in close proximity to two adjacent PCI slots thus
reducing layout complexity and placement costs in
• Adjustable Turn-On Slew Rate
• Minimum Parts Count Solution
• No Charge Pump
assembly. The HIP1011D, HIP1011E provides independent
power control to each slot and the addition of discrete power
MOSFETs and a few passive components creates two
complete power control solutions. The IC integrates the
+12V and -12V current sensing switches for each slot.
Overcurrent (OC) protection is provided by sensing the
voltage across external current-sense resistors. In addition,
on-chip references are used to monitor the +5V, +3.3V and
+12V outputs for undervoltage (UV) conditions *. The two
PWRON inputs control the state of the switches, one each
for slot A and slot B outputs. During an OC condition on any
output, or a UV condition on the +5V, +3.3V or +12V outputs
*, a LOW (0V) is asserted on the associated FLTN output
and all associated switches are latched-off. The outputs
servicing the adjacent slot are unaffected.
• 100ns Response Time to Overcurrent
• Pb-Free Available (RoHS Compliant)
Applications
• PCI Hot-Plug
Ordering Information
TEMP.
PKG.
PART NUMBER
RANGE (°C)
PACKAGE
DWG. #
HIP1011DCA*
0 to 70
0 to 70
28 Ld SSOP
M28.15
M28.15
HIP1011DCAZA*
(See Note)
28 Ld SSOP
(Pb-free)
HIP1011ECA*
0 to 70
0 to 70
28 Ld SSOP
M28.15
M28.15
The time to FLTN signal going LOW and MOSFET latch off
is user determined by a single capacitor from each FLTN pin
to ground. This added feature enables the HIP1011D,
HIP1011E to ignore system noise transients. The FLTN latch
is cleared when the PWRON input is toggled low again.
During initial power-up of the main VCC supply (+12V), the
PWRON input is inhibited from turning on the switches, and
the latch is held in the Reset state until the VCC input is
greater than 10V.
HIP1011ECAZA*
(See Note)
28 Ld SSOP
(Pb-free)
* Add “-T” suffix for tape and reel option.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020C.
HIP1011D, HIP1011E (SSOP)
Pinout
TOP VIEW
User programmability of the overcurrent threshold and turn-
on slew rate is provided. A resistor connected to the OCSET
pin programs the overcurrent threshold for both slots.
Capacitors connected to the gate pins set the turn-on rate.
M12VO_2
M12VG_2
PWRON_2
FLTN_2
VSS
12VG_2
12VO_2
12VO_1
12VG_1
OCSET 10
FLTN_1 11
PWRON_1 12
M12VG_1 13
M12VO_1 14
1
2
3
4
5
6
7
8
9
28 M12VIN_2
27 3VISEN_2
26 3VS_2
25 5VISEN_2
24 5VS_2
23 3V5VG_2
22 12VIN_2
21 12VIN_1
20 3V5VG_1
19 5VS_1
* UV references do not apply to HIP1011E.
18 5VISEN_1
17 3VS_1
16 3VISEN_1
15 M12VIN_1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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Copyright © Intersil Americas Inc. 1999, 2000, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
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