Datasheet > HI-8504PSM

HI-8504PSM

更新时间： 2024-02-13 06:14:45

品牌	Logo	应用领域
HOLTIC		驱动接口集成电路
页数	文件大小	规格书
15页	485K
描述
Line Driver,

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技术参数
数据手册

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HI-8504PSM 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.73
接口集成电路类型：	LINE DRIVER	JESD-609代码：	e0
峰值回流温度（摄氏度）：	NOT SPECIFIED	端子面层：	Tin/Lead (Sn/Pb)
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

HI-8504PSM 数据手册

HI-8500

FUNCTIONAL DESCRIPTION

Figure 2 is a block diagram of the line driver. The +5V and

-5V levels are generated from the supply voltages. Output

slope control is set by on-chip precision current sources

and capacitors.

A unity gain buffer receives the internally generated slopes

and differentially drives the ARINC line. Current is limited

by the series output resistors at each pin. There are no

fuses at the outputs of the HI-8500.

The TXIN0 and TXIN1 inputs receive logic signals from a

control transmitter chip such as the HI-3210 or FPGA.

TXAn and TXBn hold each side of the ARINC bus at

Ground until one of the inputs becomes a One. If for ex-

ample TXIN1 goes high, a charging path is enabled to 5V

on an “A” side internal capacitor while the “B” side is en-

abled to -5V. The charging current is selected by the

SLP1.5 pin. If the SLP1.5 pin is high, the capacitor is

nominally charged from 10% to 90% in 1.5µs. If SLP1.5 is

low, the rise and fall times are 10µs.

ARINC 429 requires that each line has a source imped-

ance of 37.5 Ohms. The TXA37 and TXB37 have the re-

quired resistance to directly drive the bus. Alternatively,

TXA/B10 or TXA/B0 outputs have 10 ohms or zero ohms

internally. The reduced resistance allows for external light-

ning protection circuitry to be added, while maintaining the

total output resistance at 37.5 Ohms. See Holt Applica-

tions Notes AN-300 and AN-301 for suitable, proven light-

ning protection schemes.

The HI-8500 is built using high-speed CMOS technology.

Care should be taken to ensure the V+ and V- supplies are

locally decoupled.

“A” SIDE

ONE

TXAOUT

CURRENT

CONTROL

NULL

ZERO

-5V

CONTROL

LOGIC

TX0IN

ESD

PROTECTION

AND

SLP1.5

VOLTAGE

TRANSLATION

“B” SIDE

TX1IN

ZERO

NULL

ONE

TXBOUT

CURRENT

CONTROL

-5V

CONTROL

LOGIC

FIGURE 2 - LINE DRIVER BLOCK DIAGRAM

VCC

HARDWIRED

TESTA

ROUTA

ARX0P

ARX0N

{

TESTB

DRIVEN FROM LOGIC

ROUTB

HI-8450

RINA

ARINC

HI-3200

APPLICATION INFORMATION

Channel

RINB

Figure 3 shows a possible application

of the HI-8500 interfacing an ARINC 429

transmit channel from the HI-3200.

HOST SPI

12V

V+

TXIN1

TXA37

ATX0P

ARINC

HI-8500

Channel

TXB37

ATX0N

TXIN0

SLP1.5

V-

ATXSLP0

GND

-12V

FIGURE 3 - APPLICATION DIAGRAM

HOLT INTEGRATED CIRCUITS

1 2 3 456 7 8...15

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