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HFIXF1010CCA2QE000 PDF预览

HFIXF1010CCA2QE000

更新时间: 2024-01-02 09:02:05
品牌 Logo 应用领域
英特尔 - INTEL 时钟局域网数据传输外围集成电路
页数 文件大小 规格书
144页 1843K
描述
LAN Controller, 10 Channel(s), 125MBps, CMOS, CBGA552, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-552

HFIXF1010CCA2QE000 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:552
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.74其他特性:ALSO REQUIRES 2.5V SUPPLY
地址总线宽度:11边界扫描:YES
最大时钟频率:125 MHz最大数据传输速率:125 MBps
外部数据总线宽度:32JESD-30 代码:S-CBGA-B552
长度:25 mm低功率模式:YES
串行 I/O 数:10端子数量:552
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:4.237 mm
最大供电电压:1.89 V最小供电电压:1.71 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:25 mm
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches:1

HFIXF1010CCA2QE000 数据手册

 浏览型号HFIXF1010CCA2QE000的Datasheet PDF文件第2页浏览型号HFIXF1010CCA2QE000的Datasheet PDF文件第3页浏览型号HFIXF1010CCA2QE000的Datasheet PDF文件第4页浏览型号HFIXF1010CCA2QE000的Datasheet PDF文件第5页浏览型号HFIXF1010CCA2QE000的Datasheet PDF文件第6页浏览型号HFIXF1010CCA2QE000的Datasheet PDF文件第7页 
Intel® IXF1010 10-Port 100/1000 Mbps  
Ethernet Media Access Controller  
Preliminary Datasheet  
The Intel® IXF1010 is a 10-port Ethernet Media Access Controller (MAC) that supports IEEE  
802.3 100 and 1000 Mbps applications. The device supports a System Packet Interface Level 4  
Phase 2 (SPI4-2) system interface to the network processor or ASIC, and implements the  
Reduced Gigabit Media Independent Interface (RGMII), as defined in Version 1.2a of the  
Hewlett-Packard specification for PHY connectivity. The RGMII reduces the interface pin count  
from GMII to allow for higher port densities.  
Applications  
In general, the IXF1010 is appropriate for high-end switching applications where MAC and  
PHY functions are not integrated into the system ASIC.  
High-End Ethernet Switches  
Multi-Service Ethernet Switches  
High-End Ethernet LAN/WAN Routers  
Product Features  
Supports 10 independent 100/1000 Mbps  
Internal 17.0 KB receive FIFO and 4.5 KB  
full-duplex Ethernet MAC ports  
transmit FIFO per channel  
System Packet Interface Level 4 Phase 2  
Independent enable/disable of any port  
Detection of short or overly large packets  
(SPI4-2)  
Capable of data transfers from 10.24  
Error counters for dropped and errored  
Gbps up to 12.8 Gbps  
packets  
Supports dynamic phase alignment  
Integrated termination  
CRC calculation and error detection  
Programmable option to:  
Filter packets with errors  
RGMII interface with MDIO for Ethernet  
physical connectivity  
Filter, broadcast, multicast, and unicast  
32-bit CPU interface  
RMON statistics  
address packets  
Automatically pad transmitted packets  
less than the minimum frame size  
JTAG boundary scan capable  
Compliance with IEEE 802.3 MII  
552-Ceramic Ball Grid Array (CBGA)  
Management Interface (MDIO)  
1.8 V and 2.5 V operation  
Compliance with IEEE 802.3x Standard for  
Power consumption: 480 mW per-port  
flow control  
typical  
Jumbo frame support for 9.6 KB packets  
.18 µ CMOS process technology  
Notice: This document contains preliminary information on new products. The specifications are  
subject to change without notice. Verify with your local Intel sales office that you have the latest  
datasheet before finalizing a design.  
Document #: 249839  
Revision #: 004  
Rev. Date: December 18, 2002  

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