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HEF4046BTD-T PDF预览

HEF4046BTD-T

更新时间: 2024-02-23 06:53:54
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管
页数 文件大小 规格书
15页 408K
描述
IC PHASE LOCKED LOOP, PDSO16, PLL or Frequency Synthesis Circuit

HEF4046BTD-T 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:SOP, SOP16,.25Reach Compliance Code:unknown
风险等级:5.7JESD-30 代码:R-PDSO-G16
湿度敏感等级:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:5/15 V
认证状态:Not Qualified子类别:PLL or Frequency Synthesis Circuits
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

HEF4046BTD-T 数据手册

 浏览型号HEF4046BTD-T的Datasheet PDF文件第6页浏览型号HEF4046BTD-T的Datasheet PDF文件第7页浏览型号HEF4046BTD-T的Datasheet PDF文件第8页浏览型号HEF4046BTD-T的Datasheet PDF文件第10页浏览型号HEF4046BTD-T的Datasheet PDF文件第11页浏览型号HEF4046BTD-T的Datasheet PDF文件第12页 
Philips Semiconductors  
Product specification  
HEF4046B  
MSI  
Phase-locked loop  
DESIGN INFORMATION  
CHARACTERISTIC  
USING PHASE COMPARATOR 1  
USING PHASE COMPARATOR 2  
No signal on SIGNIN  
VCO in PLL system adjusts  
to centre frequency (fo)  
VCO in PLL system adjusts to min.  
frequency (fmin  
)
Phase angle between  
SIGNIN and COMPIN  
90° at centre frequency (fo),  
approaching 0° and 180° at  
ends of lock range (2 fL)  
always 0° in lock  
(positive-going edges)  
Locks on harmonics of  
centre frequency  
yes  
no  
Signal input noise  
rejection  
high  
low  
Lock frequency  
range (2 fL)  
the frequency range of the input signal on which the loop will stay locked if it was  
initially in lock; 2 fL = full VCO frequency range = fmax fmin  
Capture frequency  
range (2 fC)  
the frequency range of the input signal on which the loop will lock if it was initially  
out of lock  
depends on low-pass  
fC = fL  
filter characteristics; fC < fL  
Centre frequency (fo)  
the frequency of the VCO when VCOIN at 12VDD  
VCO component selection  
Recommended range for R1 and R2: 10 kto 1 M; for C1: 50 pF to any practical value.  
1. VCO without frequency offset (R2 = ).  
a) Given fo: use fo with Fig.7 to determine R1 and C1.  
b) Given fmax: calculate fo from fo = 12 fmax; use fo with Fig.7 to determine R1 and C1.  
2. VCO with frequency offset.  
a) Given fo and fL : calculate fmin from the equation fmin = fo fL; use fmin with Fig.8 to determine R2 and C1; calculate  
f
f
f o + f L  
f
--m-----a--x-  
--m-----a--x-  
--------------  
--m-----a--x-  
from the equation  
=
; use  
with Fig. 9 to determine the ratio R2/R1 to obtain R1.  
fmin  
fmin  
f o f L  
fmin  
b) Given fmin and fmax: use fmin with Fig.8 to determine R2 and C1; calculate  
f
f
--m-----a--x-  
--m-----a--x-  
; use  
fmin  
fmin  
with Fig.9 to determine R2/R1 to obtain R1.  
January 1995  
9

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