The receiver section accepts four
serial electrical data streams at
1250 MBd and recovers the re-
spective original 10-bit-wide data
for each channel over a 5-pin
parallel interface. The receiver
PLL locks onto the incoming
serial signal and recovers the
high-speed serial clock and data.
The serial data is converted back
into 10-bit parallel data, option-
ally recognizing the 8B/10B
comma character to establish
byte alignment. If comma charac-
ter detection is enabled by raising
the SYNC signal high, the re-
ceiver section is able to detect
comma characters and indicate
their presence on each channel
with the appropriate SYN [0:3]
signal(s).
TC line is similar to a 6th data
line that is always toggling to
provide timing information to the
SERDES. On the RX side, the
SERDES drives four sets of 5-pin
RX data centered between the
edges of RC [0:3] [1] or
PARALLEL INPUT LATCH
For each channel, the transmitter
accepts 10-bit characters as two
groups of 5-pin single-ended
SSTL_2 parallel data at inputs
TX [0:3][0:4]. The SSTL_2 TC
clock provided by the sender of
transmit data is used for all chan-
nels as the transmit byte clock.
The TX [0:3][0:4] and TC signals
must be properly aligned, as
shown in Figure 3.
RC [0:3] [0].
For test purposes, the transceiver
provides for on-chip parallel
loopback functionality controlled
through an input pin. Addition-
ally, the byte-edge alignment
feature via detection of the posi-
tive comma (K28.5+) character
may be disabled. This may be
useful in proprietary applications
that use alternative methods to
align the parallel data.
TX PLL/CLOCK GENERATOR
The transmitter Phase Locked
Loop and Clock Generator (TX
PLL/CLOCK GENERATOR) block
generates all internal clocks
needed by the transmitter section
to perform its functions. These
clocks are based on the transmit
byte clock (TC). TC is also used
to determine the sampling win-
dow for the incoming data
HDMP-1685A Block Diagram
The recovered parallel data are
presented at SSTL_2-compatible
outputs RX [0:3] [0:4], and a pair
of 125 MHz SSTL_2 clocks,
RC [0:3] [1], and RC [0:3] [0],
that are 180 degrees out of phase
from one another and which rep-
resent the remote clock for that
channel. Rising edges of
RC [0:3] [1] and RC [0:3] [0]
may be used to latch RX data at
the destination. Alternatively,
both edges of either RC [0:3] [1]
or RC [0:3] [0] may be used to
latch RX data (DDR). When SYNC
is high, the beginning half of the
comma character shows up at the
rising edge of
The HDMP-1685A (Figure 2) is
designed to transmit and receive
10-bit 8B/10B character data
over 5-pin-wide parallel busses
via high-speed serial communica-
tion lines. The parallel data
latches. Incoming data is syn-
chronous with TC (see Figure 3).
FRAME MUX
applied to the transmitter is
The FRAME MUX accepts the
10-bit-wide parallel data from the
INPUT LATCH. Using internally
generated high-speed clocks, this
parallel data is multiplexed into
the 1250 MBd serial data
streams. The data bits are trans-
mitted sequentially, from TX [0]
to TX [4]. The leftmost bit of
K28.5 is on TX [0].
expected to be encoded per the
8B/10B encoding scheme with
special reserve characters for link
management purposes. Other
encoding schemes will also work
as long as they provide dc bal-
ance and sufficient number of
transitions. In order to accom-
plish this task, the HDMP-1685A
incorporates the following:
SERIAL OUTPUT SELECT
RC [0:3] [1].
• SSTL_2 Parallel Data I/O
• High-Speed Phase Locked
Loops
• Parallel-to-Serial Converters
• High-Speed Serial Clock and
Data Recovery Circuitry
• Comma Character Recognition
Circuitry (K28.5+)
The OUTPUT SELECT block pro-
vides a parallel loopback mode
for testing purposes. In normal
operation, PLUP is set low and
the serialized TX [0:3] [0:4] data
are placed at SO [0:3] +/-.
The timing of transmit and re-
ceive parallel data with respect to
TC and RC [0:3] [0:1] is arranged
so that the upstream protocol
device can generate and latch
data very simply. Specifically, in
the TX direction, the ASIC drives
four sets of 5-pin TX lines and the
TC line with the same timing. The
• Byte Alignment Circuitry
• Serial-to-Parallel Converter
2
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