When parallel wrap-mode is acti-
vated by setting PLUP high, the
SO [0:3]+/- pins are held static
at logic 1 and the serial output
signal reflecting TX [0:3] [0:4]
data is internally wrapped to the
INPUT SELECT block of the re-
ceiver section.
SERIAL INPUT SAMPLER
PARALLEL OUTPUT DRIVERS
The INPUT SAMPLER converts
the serial input signal into a
retimed bit stream. In order to
accomplish this, it uses the high-
speed serial clock recovered from
the RX PLL/CLOCK RECOVERY
block. This serial bit stream is
sent to the FRAME DEMUX AND
BYTE SYNC block.
The OUTPUT DRIVERS present
the recovered 10-bit character in
two groups onto the 5-pin RX
bus, properly aligned to the re-
ceive byte clock RC [0:3] [0:1] as
shown in Figure 5. These output
data buffers provide single-ended
SSTL_2 compatible signals. Un-
like the TX, where all four chan-
nels are driven with the same
transmit byte clock (TC), each
receive channel provides its own
clock aligned with its own data,
so the recovered clocks may not
be phase aligned.
SERIAL INPUT SELECT
The INPUT SELECT block deter-
mines whether the signal at
SI [0:3]+/- or the internal loop-
back serial signal is used to drive
RX [0:3] [0:4]. In normal opera-
tion, PLUP is set low and the
serial data is accepted at
FRAME DEMUX, BYTE SYNC
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit character
from the high-speed serial bit
stream. This block is also respon-
sible for recognizing the comma
character (K28.5+) of positive
disparity (0011111xxx). When
recognized, the FRAME DEMUX
AND BYTE SYNC block works
with the RX PLL/CLOCK RECOV-
ERY block to properly select the
parallel data edge out of the bit
stream so that the comma charac-
ter starts at RX[0:3][0]. When a
comma character is detected and
realignment of the receiver byte
clock RC[0:3][0:1] is necessary,
this clock is stretched, not sliv-
ered, to the next possible correct
alignment position. This clock will
be fully aligned by the start of the
second 2-byte or 4-byte ordered
set. The second comma character
received will be aligned with the
rising edge of RC[0:3][1].
SI [0:3]+/-.
SSTL_2 COMPATIBILITY
HDMP-1685A works with proto-
col devices whose VDDQ voltage
is nominally set at 2.5 Volts.
RX [0:3][0:4], RC [0:3][0:1] pins
generate output voltages that are
compatible with the SSTL_2
standard (EIA/JESD8-9). In addi-
tion, these devices provide a
VREFR output pin allowing the
receiving device to differentially
detect a high or a low. The
devices receive inputs on their
TX [0:3][0:4] and TC pins that
are also SSTL_2 compatible. The
VREFT input pin is driven by a
voltage divider whose supply
voltage is at the same level as the
VDDQ supply of the protocol
device. This allows differential
detection of a high or a low at TX
parallel inputs.
When PLUP is set high, the out-
going high-speed serial signal is
internally looped back from the
transmitter section to the receiver
section. This feature allows par-
allel loopback testing, exclusive
of the transmission medium.
RX PLL/CLOCK RECOVERY
The RX PLL/CLOCK RECOVERY
block is responsible for frequency
and phase locking onto the in-
coming serial data stream and
recovering the bit and byte
clocks. It does this by continually
frequency locking onto the
125 MHz reference clock, and
then phase locking onto the se-
lected input data stream. An
internal signal detection circuit
monitors the presence of the
input, and invokes the phase
detection once the minimum
differential input signal level is
supplied (AC Electrical
Comma characters of positive
disparity must not be transmitted
in consecutive bytes to allow the
receiver byte clocks to maintain
their proper recovered
frequencies.
Specifications).
Once bit locked, the receiver
generates the high-speed sam-
pling clock at 1250 MHz for the
input sampler.
3
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