HDC3020-Q1
SNAS817 – JUNE 2021
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(4) Based on THB (temperature humidity bias) testing. Excludes the impact of dust, gas phase solvents and other contaminents such as
vapors from packaging materials, adhesives, or taptes, etc.
(5) The hysteresis value is the difference between the RH measurement in a rising and falling RH environment, at a specific RH point
(6) Actual response times will vary dependent on system thermal mass and air-flow
(7) Time for the RH output to change by 63% of the total RH change after a step change in environmental humidity
(8) Measurement duration includes the time to measure RH plus Temp
(9) IDD_AVG_EQN = measuruement freq x IDD_ACTIVE x tmeas+ Isleep x (1- (measurement freq x tmeas))
6.6 Switching Characteristics
TA = -40°C to 125°C and VDD = 1.62V to 5.50V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
SCL, SDA PINS
fSCL
SCL clock frequency(1)
0
0.6
1.3
100
0
1
MHz
µs
tHIGH
High period of the SCL clock(1)
LOW period of the SCL clock(1)
Setup Time: Data(1)
tLOW
µs
tSU;DAT
tHD;DAT
tSU;STA
tHD;STA
tSU;STO
tR;SCL
ns
Hold Time: Data(1)
µs
Set-up time: Repeated START condition(1)
Hold time: Repeated START condition(1) (2)
Set-up time: STOP condition(1)
Rise Time: SCL(1)
0.6
0.6
0.6
µs
µs
µs
300 ns
300 ns
300 ns
300 ns
µs
tR;SDA
Rise Time: SDA(1)
tF;SCL
Fall Time: SCL(1)
20*(VDD/5.5V)
20*(VDD/5.5V)
1.3
tF;SDA
Fall Time: SDA(1)
tBUF
Bus free time between a STOP and START condition(1)
Data valid time(1) (3)
tVD;DAT
tVD;ACK
RESET
tRESET_NPW
0.9 µs
0.9 µs
Data valid acknowledge time(1) (4)
Negative pulse width to trigger hard reset
1
µs
EEPROM (T, RH OFFSET)
tOS_PROG
Offset Programming Time
10
15 ms
(1) Guaranteed by design/characterization; not production tested
(2) After this period, the first clock pulse is generated
(3) Time for data signal from SCL low to SDA output (high to low, depending on which is worse)
(4) Time for acknowledement signal from SCL low to SDA output (high or low, depending on which is worse)
6.7 Timing Diagram
tLOW
tR
tF
tHIGH
VIH
SCL
VIL
tSU;STO
tHD;DAT
tVD;DAT
tSU;STA
tHD;STA
tBUF
tSU;DAT
VIH
VIL
SDA
P
S
S
P
Figure 6-1. HDC3020-Q1 I2C Timing Diagram
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