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HD74HC93RPEL PDF预览

HD74HC93RPEL

更新时间: 2024-02-18 20:53:00
品牌 Logo 应用领域
瑞萨 - RENESAS 计数器触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
8页 102K
描述
4-bit Binary Counter

HD74HC93RPEL 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:3.95 X 8.65 MM, 1.27 MM PITCH, PLASTIC, SOP-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.18
Is Samacsys:N其他特性:1 FUNCTION WITH ONE INPUT BIT
计数方向:UP系列:HC/UH
JESD-30 代码:R-PDSO-G14长度:8.65 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:21000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
湿度敏感等级:1位数:3
功能数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):225电源:2/6 V
传播延迟(tpd):425 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Counters
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:3.95 mm
Base Number Matches:1

HD74HC93RPEL 数据手册

 浏览型号HD74HC93RPEL的Datasheet PDF文件第2页浏览型号HD74HC93RPEL的Datasheet PDF文件第3页浏览型号HD74HC93RPEL的Datasheet PDF文件第4页浏览型号HD74HC93RPEL的Datasheet PDF文件第5页浏览型号HD74HC93RPEL的Datasheet PDF文件第6页浏览型号HD74HC93RPEL的Datasheet PDF文件第7页 
HD74HC93  
4-bit Binary Counter  
REJ03D0557-0200  
(Previous ADE-205-430)  
Rev.2.00  
Oct 06, 2005  
Description  
The HD74HC93 is a 4-bit ripple type counter consisting of four master/slave flip-flops that are internally connected to  
provide separate divide-by-two and divide-by-eight sections. Each section has a separate clock input which initiates  
state changes of the counter on the high-to-low clock transition. State changes of the Q outputs do not occur  
simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and  
should not be used as clocks or as strobes except when gated with the clock of the HD74HC93. QA is the output of the  
divide-by-two section; QB, QC, and QD are the binary outputs of the divide-by-eight section.  
A gated AND asynchronous reset is provided which resets all the flip-flops.  
Because the output from the divide-by-two section is not internally connected to the succeeding stages, the devices may  
be operated in various counting modes:  
1. A 4-bit ripple counter – The QA output must be externally connected to the clock B input. The input count pulses  
are applied to the clock A input. Simultaneous divisions of 2, 4, 8 and 16 are performed at the QA, QB, QC and QD  
outputs.  
2. A 3-bit ripple counter – The input count pulses are applied to the clock B input. Simultaneous frequency divisions  
of 2, 4 and 8 are available at the QB, QC and QD outputs. Independent use of the first flip-flop is available if the reset  
function coincides with reset of the 3-bit ripple-through counter.  
Features  
High Speed Operation: tpd (A to QA) = 13 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
DILP-14 pin  
PRDP0014AB-B  
(DP-14AV)  
HD74HC93P  
P
PRSP0014DF-B  
(FP-14DAV)  
HD74HC93FPEL  
HD74HC93RPEL  
SOP-14 pin (JEITA)  
SOP-14 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (2,500 pcs/reel)  
PRSP0014DE-A  
(FP-14DNV)  
Note: Please consult the sales office for the above package availability.  
Function Table  
Reset/Count Function Table  
Reset Inputs  
Outputs  
R0(1)  
H
R0(2)  
H
QD  
QC  
QB  
QA  
L
L
L
L
L
X
Count  
Count  
X
L
Rev.2.00, Oct 06, 2005 page 1 of 7  

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