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HD74HC95P PDF预览

HD74HC95P

更新时间: 2024-02-05 06:14:49
品牌 Logo 应用领域
日立 - HITACHI 输入元件光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 42K
描述
Parallel In Parallel Out, HC/UH Series, 4-Bit, Right Direction, True Output, CMOS, PDIP14, DP-14

HD74HC95P 数据手册

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HD74HC95  
4-bit Parallel Access Shift Register  
Description  
This 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs.  
The register has three mode operation:  
Parallel (broadside) load  
Shift right (the direction QA toward QD)  
Shift left (the direction QD toward QA)  
Parallel loading is accomplished by applying the four bits of data and taking the mode conrol input high.  
The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of  
the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is accomplished on the  
high-to-low transition of clock-1 when the mode control is low; shift left is accomplished on the high-to-  
low transition of clock-2 when the mode control is high by connecting the output of each flip-flop (QD to  
input C, etc.) and serial data is entered at input D. The clock input may be applied commonly to clock-1  
and clock-2 if both modes can be clocked from the same source. Changes at the mode control input should  
normally be made while both clock inputs are low: however, conditions described in the last three lines of  
the function table will also ensure that register contents are protected.  
Features  
High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF)  
High Output Current: Fanout of 10 LSTTL Loads  
Wide Operating Voltage: VCC = 2 to 6 V  
Low Input Current: 1 µA max  
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)  

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