HD74HC95RP-EL

更新时间： 2024-01-01 07:51:41

品牌	Logo	应用领域
瑞萨 - RENESAS		移位寄存器
页数	文件大小	规格书
7页	90K
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数据手册

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HD74HC95RP-EL 数据手册

HD74HC95

8-bit Shift Register

REJ03D0558-0200

(Previous ADE-205-431)

Rev.2.00

Oct 06, 2005

Description

This 4-bit register features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register

has three mode operation:

•

Parallel (broadside) load

Shift right (the direction Q_Atoward Q_D)

Shift left (the direction Q_Dtoward Q_A)

Parallel loading is accomplished by applying the four bits of data and taking the mode control input high. The data is

loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input.

During loading, the entry of serial data is inhibited. Shift right is accomplished on the high-to-low transition of clock-1

when the mode control is low; shift left is accomplished on the high-to-low transition of clock-2 when the mode control

is high by connecting the output of each flip-flop (Q_Dto input C, etc.) and serial data is entered at input D. The clock

input may be applied commonly to clock-1 and clock-2 if both modes can be clocked from the same source. Changes at

the mode control input should normally be made while both clock inputs are low: however, conditions described in the

last three lines of the function table will also ensure that register contents are protected.

Features

•

High Speed Operation: t_pd(Clock to Q) = 17 ns typ (C_L= 50 pF)

High Output Current: Fanout of 10 LSTTL Loads

Wide Operating Voltage: V_CC= 2 to 6 V

Low Input Current: 1 µA max

Low Quiescent Supply Current: I_CC(static) = 4 µA max (Ta = 25°C)

Ordering Information

Package Code

(Previous Code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

Package Type

DILP-14 pin

SOP-14 pin (JEDEC)

PRDP0014AB-B

(DP-14AV)

HD74HC95P

—

PRSP0014DE-A

(FP-14DNV)

HD74HC95RPEL

EL (2,500 pcs/reel)

Rev.2.00, Oct 06, 2005 page 1 of 6

12 3 4 5 6 7

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