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HCPL-5201#300 PDF预览

HCPL-5201#300

更新时间: 2024-02-16 07:59:59
品牌 Logo 应用领域
安捷伦 - AGILENT 输出元件光电
页数 文件大小 规格书
12页 294K
描述
Logic IC Output Optocoupler, 1-Element, 1500V Isolation, 5MBps, HERMETIC, GULL WING, CERAMIC, DIP-8

HCPL-5201#300 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:HERMETIC, GULL WING, CERAMIC, DIP-8Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8541.40.80.00
风险等级:5.24其他特性:TTL COMPATIBLE, HIGH RELIABILITY
配置:COMPLEX标称数据速率:5 MBps
最大正向电流:0.008 A最大绝缘电压:1500 V
JESD-609代码:e0安装特点:SURFACE MOUNT
元件数量:1最大通态电流:0.015 A
最高工作温度:125 °C最低工作温度:-55 °C
光电设备类型:LOGIC IC OUTPUT OPTOCOUPLER最大功率耗散:0.2 W
标称响应时间:3e-7 ns子类别:Optocoupler - IC Outputs
最小供电电压:4.5 V标称供电电压:20 V
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
Base Number Matches:1

HCPL-5201#300 数据手册

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8
Typical Characteristics (cont’d.)  
All typical values are at T = 25°C, VCC = 5 V, IF(ON) = 5 mA, unless otherwise specified.  
A
Single Channel Product Only  
Parameter  
Symbol Typ.  
Units  
Test Conditions  
Fig. Notes  
Output Enable Time to Logic High  
tPZH  
tPZL  
tPHZ  
tPLZ  
30  
30  
45  
55  
ns  
8
Output Enable Time to Logic Low  
Output Disable Time from Logic High  
Output Disable Time from Logic Low  
ns  
ns  
ns  
8
8
8
Dual and Quad Channel Products Only  
RH = 45%, TA = 25°C,  
Input-Input Insulation Leakage Current  
II-I  
0.5  
nA  
V
I-I = 500 V, t = 5 s  
9
9
9
Resistance (Input-Input)  
RI-I  
1013  
VI-I = 500 V  
f = 1 MH  
Capacitance (Input-Input)  
CI-I  
1.5  
pF  
Notes:  
1. Peak Forward Input Current pulse width < 50 µs at 1 KHz maximum repetition rate.  
2. Each channel of a multichannel device.  
3. Duration of output short circuit time not to exceed 10 ms.  
4. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads  
or terminals shorted together.  
5. This is a momentary withstand test, not an operating condition.  
6. CML is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO  
< 0.8 V). CM is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic  
high state (V H> 2.0 V).  
7. tPHL propagatOion delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge  
of the output pulse. The t propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V  
point on the trailing edgePoLHf the output pulse.  
8. Measured between each input pair shorted together and all output connections for that channel shorted together.  
9. Measured between adjacent input pairs shorted together for each multichannel device.  
10. Zero-bias capacitance measured between the LED anode and cathode.  
11. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD, Class H and Class K parts receive 100% testing at 25, 125,  
and –55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).  
12. Parameters are tested as part of device initial characterization and after design and process changes. Parameters guaranteed to limits  
specified for all lots not specifically tested.  
Figure 1. Typical Logic Low Output  
Voltage vs. Temperature.  
Figure 2. Typical Logic High Output  
Current vs. Temperature.  

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