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HCF4522BC1 PDF预览

HCF4522BC1

更新时间: 2024-11-18 22:55:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 计数器触发器逻辑集成电路输出元件
页数 文件大小 规格书
6页 205K
描述
PROGRAMMABLE BCD DIVIDER-BY-N COUNTER

HCF4522BC1 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:PLASTIC, LCC-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
其他特性:TCO OUTPUT; GATED CLOCK计数方向:DOWN
系列:4000/14000/40000JESD-30 代码:S-PQCC-J20
JESD-609代码:e3长度:8.965 mm
负载/预设输入:YES逻辑集成电路类型:DECADE COUNTER
工作模式:SYNCHRONOUS位数:4
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC20,.4SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:3/18 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Counters
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.965 mmBase Number Matches:1

HCF4522BC1 数据手册

 浏览型号HCF4522BC1的Datasheet PDF文件第2页浏览型号HCF4522BC1的Datasheet PDF文件第3页浏览型号HCF4522BC1的Datasheet PDF文件第4页浏览型号HCF4522BC1的Datasheet PDF文件第5页浏览型号HCF4522BC1的Datasheet PDF文件第6页 
HCC4522B  
HCF4522B  
PROGRAMMABLE BCD DIVIDER-BY-N COUNTER  
PRODUCT PREVIEW  
.
.
.
.
VERY LOW QUIESCENT CURRENT  
HIGH NOISE IMMUNITY  
SUPPLY VOLTAGE RANGE 3V TO 18V  
INTERNALLY SYNCHRONOUS FOR HIGH IN-  
TERNAL AND EXTERNAL SPEEDS  
5.0MHz COUNTING RATE  
INCREMENTED ON POSITIVE TRANSITION  
OF CLOCK OR NEGATIVE TRANSITION OF  
CLOCK INHIBIT  
.
.
EY  
F
(Plastic Package)  
(Ceramic Frit Seal Package)  
.
ASYNCHRONOUS PRESET ENABLE  
M1  
C1  
(Micro Package)  
(Plastic Chip Carrier)  
ORDER CODES :  
HCC4522 BF  
HCF4522 BEY  
HCF4522 BM1  
HCF4522 BC1  
PIN CONNECTION (top view)  
DESCRIPTION  
The HCC4522B and HCF4522B are monolithic in-  
tegrated circuits, available in 16-lead dual-in-line  
plastic or ceramic packages and plastic micro pack-  
ages.  
The HCC4522B and HCF4522B are programm-  
able, BCD down counters with a decoded 0” state  
output for divide-by-N applications. The counters  
are cascadable. In single stage applications the ”0”  
output is applied to the Preset Enable input. The  
cascade feedback input allowscascade divide-by-N  
operation with no additional gates required. The  
clock Inhibit input allows disabling of the pulse  
counting function.  
Applications for these programmable divide-by-N  
counters include frequency synthesizers, phase-  
locked loops and other frequency dividing circuits  
where low power and/or high noise immunity is re-  
quired.  
September 1990  
1/6  

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