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HCF4042B PDF预览

HCF4042B

更新时间: 2024-09-28 22:56:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
13页 303K
描述
QUAD CLOCKED ”D” LATCH

HCF4042B 数据手册

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HCC/HCF4042B  
QUAD CLOCKED ”D” LATCH  
.
.
.
.
.
CLOCK POLARITY CONTROL  
Q AND Q OUTPUTS  
COMMON CLOCK  
LOW POWER TTL COMPATIBLE  
STANDARDIZED SYMMETRICAL OUTPUT  
CHARACTERISTICS  
QUIESCENT CURRENT SPECIFIED TO 20V  
FOR HCC DEVICE  
5V, 10V, AND 15V PARAMETRIC RATINGS  
INPUT CURRENT OF 100nA AT 18V AND 25°C  
FOR HCC DEVICE  
100% TESTED FOR QUIESCENT CURRENT  
MEETS ALLREQUIREMENTS OF JEDECTEN-  
TATIVESTANDARDN°13A, ”STANDARD SPE-  
CIFICATIONS FOR DESCRIPTION OF ”B”  
SERIES CMOS DEVICES”  
EY  
F
.
(Plastic Package)  
(Ceramic Package)  
.
.
.
.
C1  
M1  
(Plastic Chip Carrier)  
(Micro Package)  
ORDER CODES :  
HCC4042BF  
HCF4042BM1  
HCF4042BEY  
HCF4042BC1  
PIN CONNECTIONS  
DESCRIPTION  
The HCC4042B (extended temperature range) and  
HCF4042B (intermediate temperature range) are  
monolithic integrated circuit, available in 16-lead  
dual in-line plastic or ceramic package and plastic  
micro package.  
The HCC/HCF4042B types contain four latch cir-  
cuits, each strobed by a common clock. Com-  
plementary buffered outputs are available from  
each circuit. The impedance of the n- and p-channel  
output devices is balanced and all outputs are elec-  
trically identical.  
Information present at the data input is transferred  
to outputs Q and Q during the CLOCK level which  
is programmed by the POLARITY input. For PO-  
LARITY= 0 the transfer occurs during the 0 CLOCK  
level and for POLARITY = 1 the transfer occurs dur-  
ing the 1 CLOCK level. The outputs follow the data  
input providing the CLOCK and POLARITY levels  
defined above are present. When a CLOCK transi-  
tion occurs (positive for POLARITY= 0 and negative  
for POLARITY = 1) the information present at the  
input during the CLOCK transition is retained at the  
outputs until an opposite CLOCK transition occurs.  
June 1989  
1/13  

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