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HB52D168DC-A6F PDF预览

HB52D168DC-A6F

更新时间: 2023-06-15 00:00:00
品牌 Logo 应用领域
日立 - HITACHI 动态存储器
页数 文件大小 规格书
68页 302K
描述
Synchronous DRAM Module, 16MX64, 6ns, CMOS, DIMM-144

HB52D168DC-A6F 数据手册

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HB52D168DC-F  
128 MB Unbuffered SDRAM S.O.DIMM  
16-Mword ´ 64-bit, 100 MHz Memory Bus, 2-Bank Module  
(8 pcs of 8 M ´ 16 components)  
PC100 SDRAM  
ADE-203-1092B (Z)  
Rev. 1.0  
Mar. 28, 2000  
Description  
The HB52D168DC is a 8M ´ 64 ´ 2 banks Synchronous Dynamic RAM Small Outline Dual In-line  
Memory Module (S.O.DIMM), mounted 8 pieces of 128-Mbit SDRAM (HM5212165FTD) sealed in TSOP  
package and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the product is 144-  
pin Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density mounting  
possible without surface mount technology. It provides common data inputs and outputs. Decoupling  
capacitors are mounted beside TSOP on the module board.  
Features  
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Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM  
: Intel PCB Reference design (Rev.1.0)  
144-pin Zig Zag Dual tabs socket type (dual lead out)  
¾ Outline: 67.60 mm (Length) ´ 31.75 mm (Height) ´ 3.80 mm (Thickness)  
¾ Lead pitch: 0.80 mm  
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3.3 V power supply  
Clock frequency: 100 MHz (max)  
LVTTL interface  
Data bus width: ´ 64 Non parity  
Single pulsed RAS  
4 Banks can operates simultaneously and independently  
Burst read/write operation and burst read/single write operation capability  
Programmable burst length : 1/2/4/8/full page  

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