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GS880F32CT-6.5IV PDF预览

GS880F32CT-6.5IV

更新时间： 2024-02-02 15:31:31
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
19页 296K
描述
Cache SRAM, 256KX32, 6.5ns, CMOS, PQFP100, TQFP-100

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GS880F32CT-6.5IV 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.33Is Samacsys：N
最长访问时间：6.5 ns其他特性：FLOW-THROUGH ARCHITECTURE, IT ALSO OPERATES WITH 2.3 V TO 2.7 V SUPPLY
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：8388608 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.8/2.5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.045 A
最小待机电流：1.7 V子类别：SRAMs
最大压摆率：0.145 mA最大供电电压 (Vsup)：2 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

GS880F32CT-6.5IV 数据手册

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GS880F18/32/36CT-xxxIV  
5.5 ns–7.5 ns  
512K x 18, 256K x 32, 256K x 36  
9Mb Sync Burst SRAMs  
100-Pin TQFP  
Industrial Temp  
1.8 V or 2.5 V V  
DD  
1.8 V or 2.5 V I/O  
Designing For Compatibility  
The JEDEC standard for Burst RAMS calls for a FT mode pin  
option on Pin 14. Board sites for flow through Burst RAMS  
Features  
• Flow Through operation; Pin 14 = No Connect  
• 1.8 V or 2.5 V +10%/–10% core power supply  
• 1.8 V or 2.5 V I/O supply  
should be designed with V connected to the FT pin location  
SS  
to ensure the broadest access to multiple vendor sources.  
Boards designed with FT pin pads tied low may be stuffed with  
GSI’s pipeline/flow through-configurable Burst RAMs or any  
vendor’s flow through or configurable Burst SRAM. Boards  
designed with the FT pin location tied high or floating must  
employ a non-configurable flow through Burst RAM, like this  
RAM, to achieve flow through functionality.  
• LBO pin for Linear or Interleaved Burst mode  
• Internal input resistors on mode pins allow floating mode pins  
• Byte Write (BW) and/or Global Write (GW) operation  
• Internal self-timed write cycle  
• Automatic power-down for portable applications  
• JEDEC-standard 100-lead TQFP package  
• RoHS-compliant 100-lead TQFP package available  
Functional Description  
Byte Write and Global Write  
Byte write operation is performed by using Byte Write enable  
(BW) input combined with one or more individual byte write  
signals (Bx). In addition, Global Write (GW) is available for  
writing all bytes at one time, regardless of the Byte Write  
control inputs.  
Applications  
The GS880F18/32/36CT-xxxIV is a 9,437,184-bit (8,388,608-  
bit for x32 version) high performance synchronous SRAM  
with a 2-bit burst address counter. Although of a type  
originally developed for Level 2 Cache applications supporting  
high performance CPUs, the device now finds application in  
synchronous SRAM applications, ranging from DSP main  
store to networking chip set support.  
Sleep Mode  
Low power (Sleep mode) is attained through the assertion  
(High) of the ZZ signal, or by stopping the clock (CK).  
Memory data is retained during Sleep mode.  
Controls  
Addresses, data I/Os, chip enables (E1, E2, E3), address burst  
control inputs (ADSP, ADSC, ADV), and write control inputs  
(Bx, BW, GW) are synchronous and are controlled by a  
positive-edge-triggered clock input (CK). Output enable (G)  
and power down control (ZZ) are asynchronous inputs. Burst  
cycles can be initiated with either ADSP or ADSC inputs. In  
Burst mode, subsequent burst addresses are generated  
internally and are controlled by ADV. The burst address  
counter may be configured to count in either linear or  
interleave order with the Linear Burst Order (LBO) input. The  
Burst function need not be used. New addresses can be loaded  
on every cycle with no degradation of chip performance.  
Core and Interface Voltages  
The GS880F18/32/36CT-xxxIV operates on a 1.8 V or 2.5 V  
power supply. All input are 2.5 V and 1.8 V compatible.  
Separate output power (V  
) pins are used to decouple  
DDQ  
output noise from the internal circuits and are 2.5 V and 1.8 V  
compatible.  
Paramter Synopsis  
-5.5I  
-6.5I  
-7.5I  
Unit  
tKQ  
5.5  
5.5  
6.5  
6.5  
7.5  
7.5  
ns  
ns  
tCycle  
Flow Through  
2-1-1-1  
Curr (x18)  
Curr (x32/x36)  
155  
175  
135  
160  
133  
145  
mA  
mA  
Rev: 1.04 6/2012  
1/19  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  
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