GS880F32T-12

更新时间： 2024-02-01 15:02:02

品牌	Logo	应用领域
GSI		存储静态存储器
页数	文件大小	规格书
25页	351K
描述
512K x 18, 256K x 36 8Mb Sync Burst SRAMs

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技术参数
数据手册

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GS880F32T-12 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP, QFP100,.63X.87	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.8
最长访问时间：	11.5 ns	其他特性：	FLOW-THROUGH ARCHITECTURE
最大时钟频率 (fCLK)：	83 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
长度：	20 mm	内存密度：	8388608 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	32
湿度敏感等级：	3	功能数量：	1
端子数量：	100	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	256KX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	2.5/3.3,3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大待机电流：	0.04 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.18 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GS880F32T-12 数据手册

Preliminary

GS880F18/36T-10/11/11.5/12/14

100 Pin TQFP

Commercial Temp

Industrial Temp

10ns - 14ns

3.3V VDD

3.3V & 2.5V I/O

512K x 18, 256K x 36

8Mb Sync Burst SRAMs

broadest access to multiple vendor sources. Boards designed with FT

pin pads tied low may be stuffed with GSI’s Pipeline/Flow through

configurable Burst RAMS or any vendor’s Flow through or

configurable Burst SRAM. Bumps designed with the FT pin location

tied High or floating must employ a non-configurable Flow through

Burst RAM, like this RAM, to achieve Flow through functionality.

Features

• Flow through mode operation.

• 3.3V +10%/-5% Core power supply.

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

Default to Interleaved Pipelined Mode.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

88018/32/36TByte Write and Global Write

Byte write operation is performed by using byte write enable (BW)

input combined with one or more individual byte write signals (Bx). In

addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

• Automatic power-down for portable applications.

• 100-lead TQFP package

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

-10

-11

-11.5

-12

-14

Flow Through

2-1-1-1

10ns 11ns 11.5ns 12ns 14ns

10ns 15ns 15ns 15ns 15ns

225mA 180mA 180mA 180mA 175mA

Core and Interface Voltages

The GS880F18/32/36T operates on a 3.3V power supply and all

tCycle

inputs/outputs are 3.3V and 2.5V compatible. Separate output power

) pins are used to de-couple output noise from the internal

DDQ

circuit.

Functional Description

Applications

The GS880F18/32/36T is a 9,437,184 bit (8,388,608 bit for x32

version) high performance synchronous SRAM with a 2 bit burst

address counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPU’s, the device

now finds application in synchronous SRAM applications ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/O’s, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive edge triggered

clock input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Designing For Compatibility

The JEDEC Standard for Burst RAMS calls for a FT mode pin option

(pin 14 on TQFP). Board sites for Flow through Burst RAMS should

be designed with VSS connected to the FT pin location to ensure the

Rev: 1.03 3/2000

1/25

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...25

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与GS880F32T-12相关器件

型号	品牌	获取价格	描述	数据表
GS880F32T-12I	GSI	获取价格	Cache SRAM, 256KX32, 11.5ns, CMOS, PQFP100, TQFP-100
GS880F32T-12IT	GSI	获取价格	Cache SRAM, 256KX32, 11.5ns, CMOS, PQFP100, TQFP-100
GS880F32T-12T	GSI	获取价格	暂无描述
GS880F32T-14	GSI	获取价格	512K x 18, 256K x 36 8Mb Sync Burst SRAMs
GS880F32T-14I	GSI	获取价格	Cache SRAM, 256KX32, 12ns, CMOS, PQFP100, TQFP-100
GS880F32T-14IT	GSI	获取价格	Cache SRAM, 256KX32, 12ns, CMOS, PQFP100, TQFP-100
GS880F32T-14T	GSI	获取价格	Cache SRAM, 256KX32, 12ns, CMOS, PQFP100, TQFP-100
GS880F36AGT-5.5I	GSI	获取价格	Cache SRAM, 256KX36, 5.5ns, CMOS, PQFP100, TQFP-100
GS880F36AGT-5.5T	GSI	获取价格	Cache SRAM, 256KX36, 5.5ns, CMOS, PQFP100, TQFP-100
GS880F36AGT-6IT	GSI	获取价格	Cache SRAM, 256KX36, 6ns, CMOS, PQFP100, TQFP-100

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