Datasheet > GS8662T36BGD-300

GS8662T36BGD-300

更新时间： 2024-02-06 15:41:24

品牌	Logo	应用领域
GSI		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
35页	1176K
描述
DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

GS8662T36BGD-300 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA, BGA165,11X15,40	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	Factory Lead Time：	8 weeks
风险等级：	4.59	最长访问时间：	0.45 ns
其他特性：	PIPELINED ARCHITECTURE, LATE WRITE	最大时钟频率 (fCLK)：	300 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e1	长度：	15 mm
内存密度：	75497472 bit	内存集成电路类型：	DDR SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	1.5/1.8,1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.625 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	13 mm
Base Number Matches：	1

GS8662T36BGD-300 数据手册

GS8662T08/09/18/36BD-400/350/333/300/250

400 MHz–250 MHz

165-Bump BGA

Commercial Temp

Industrial Temp

72Mb SigmaDDR-II^TM

Burst of 2 SRAM

1.8 V V

1.8 V and 1.5 V I/O

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Features

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36, x18 and x9) and Nybble Write (x8) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

Each internal read and write operation in a SigmaDDR-II B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed.

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb

devices

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

When a new address is loaded into a x18 or x36 version of the

part, A0 is used to initialize the pointers that control the data

multiplexer / de-multiplexer so the RAM can perform "critical

word first" operations. From an external address point of view,

regardless of the starting point, the data transfers always follow

the same sequence {0, 1} or {1, 0} (where the digits shown

represent A0).

SigmaDDR™ Family Overview

The GS8662T08/09/18/36BD are built in compliance with the

SigmaDDR-II SRAM pinout standard for Common I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662T08/09/18/36BD SigmaDDR-II SRAMs

are just one element in a family of low power, low voltage

HSTL I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Unlike the x18 and x36 versions, the input and output data

multiplexers of the x8 and x9 versions are not preset by

address inputs and therefore do not allow "critical word first"

operations. The address fields of the x8 and x9 SigmaDDR-II

B2 RAMs are one address pin less than the advertised index

depth (e.g., the 8M x 8 has an 4M addressable index, and A0 is

not an accessible address pin).

Clocking and Addressing Schemes

The GS8662T08/09/18/36BD SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

Parameter Synopsis

-400

2.5 ns

0.45 ns

-350

2.86 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

tKHKH

tKHQV

Rev: 1.02c 12/2011

1/35

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...35

下载PDF

与GS8662T36BGD-300相关器件

型号	品牌	描述	获取价格	数据表
GS8662T36BGD-300I	GSI	165 BGA	获取价格
GS8662T36BGD-333	GSI	165 BGA	获取价格
GS8662T36BGD-333I	GSI	165 BGA	获取价格
GS8662T36BGD-333T	GSI	DDR SRAM, 2MX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	获取价格
GS8662T36BGD-400	GSI	165 BGA	获取价格
GS8662T36BGD-400I	GSI	165 BGA	获取价格

与GS8662T36BGD-300相关文章

STM32H743技术深度剖析与应用案例探索
2024-05-30

15
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
2024-05-30

15
74HC14芯片资料介绍：性能特性分析、引脚介绍
2024-05-30

13
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
2024-05-30

10

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8662T36BGD-300

GS8662T36BGD-300 技术参数

GS8662T36BGD-300 数据手册

与GS8662T36BGD-300相关器件

与GS8662T36BGD-300相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GS8662T36BGD-300

GS8662T36BGD-300 技术参数

GS8662T36BGD-300 数据手册

与GS8662T36BGD-300相关器件

与GS8662T36BGD-300相关文章

您还可以找

您在本页遇到什么问题？