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GS8662DT37BGD-333I PDF预览

GS8662DT37BGD-333I

更新时间: 2024-02-08 19:57:10
品牌 Logo 应用领域
GSI 静态存储器内存集成电路
页数 文件大小 规格书
28页 505K
描述
72Mb SigmaQuad-IITM 72Mb SigmaQuad-IITM

GS8662DT37BGD-333I 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:BGA包装说明:LBGA,
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
Factory Lead Time:8 weeks风险等级:5.69
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165长度:15 mm
内存密度:75497472 bit内存集成电路类型:QDR SRAM
内存宽度:36功能数量:1
端子数量:165字数:2097152 words
字数代码:2000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX36封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:1.4 mm
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:13 mmBase Number Matches:1

GS8662DT37BGD-333I 数据手册

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GS8662DT07/10/19/37BD-450/400/350/333/300  
450 MHz–300 MHz  
72Mb SigmaQuad-II+TM  
Burst of 4 SRAM  
165-Bump BGA  
Commercial Temp  
Industrial Temp  
1.8 V V  
DD  
1.8 V and 1.5 V I/O  
are just one element in a family of low power, low voltage  
HSTL I/O SRAMs designed to operate at the speeds needed to  
implement economical high performance networking systems.  
Features  
• 2.0 Clock Latency  
• Simultaneous Read and Write SigmaQuad™ Interface  
• JEDEC-standard pinout and package  
• Dual Double Data Rate interface  
• Byte Write controls sampled at data-in time  
• Burst of 4 Read and Write  
• Dual-Range On-Die Termination (ODT) on Data (D), Byte  
Write (BW), and Clock (K, K) inputs  
• 1.8 V +100/–100 mV core power supply  
• 1.5 V or 1.8 V HSTL Interface  
Clocking and Addressing Schemes  
The GS8662DT07/10/19/37BD SigmaQuad-II+ SRAMs are  
synchronous devices. They employ two input register clock  
inputs, K and K. K and K are independent single-ended clock  
inputs, not differential inputs to a single differential clock input  
buffer.  
• Pipelined read operation  
• Fully coherent read and write pipelines  
• ZQ pin for programmable output drive strength  
• Data Valid Pin (QVLD) Support  
• IEEE 1149.1 JTAG-compliant Boundary Scan  
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package  
• RoHS-compliant 165-bump BGA package available  
Each internal read and write operation in a SigmaQuad-II+ B4  
RAM is four times wider than the device I/O bus. An input  
data bus de-multiplexer is used to accumulate incoming data  
before it is simultaneously written to the memory array. An  
output data multiplexer is used to capture the data produced  
from a single memory array read and then route it to the  
appropriate output drivers as needed. Therefore the address  
field of a SigmaQuad-II+ B4 RAM is always two address pins  
less than the advertised index depth (e.g., the 8M x 8 has a 2M  
addressable index).  
SigmaQuadFamily Overview  
The GS8662DT07/10/19/37BD are built in compliance with  
the SigmaQuad-II+ SRAM pinout standard for Separate I/O  
synchronous SRAMs. They are 75,497,472-bit (72Mb)  
SRAMs. The GS8662DT07/10/19/37BD SigmaQuad SRAMs  
Parameter Synopsis  
-450  
-400  
2.5 ns  
0.45 ns  
-350  
2.86 ns  
0.45 ns  
-333  
-300  
tKHKH  
tKHQV  
2.22 ns  
0.45 ns  
3.0 ns  
0.45 ns  
3.3 ns  
0.45 ns  
Rev: 1.00b 8/2017  
1/28  
© 2011, GSI Technology  
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.  

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