Datasheet > GS8182T37BD-300

GS8182T37BD-300

更新时间： 2023-12-06 20:13:31

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
27页	1119K
描述
165 BGA

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数据手册

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GS8182T37BD-300 数据手册

GS8182T19/37BD-435/400/375/333/300

JTAG TAP Instruction Set Summary

SAMPLE/PRELOAD

100

101

110

111

Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.

GSI

GSI private instruction.

BYPASS

Places Bypass Register between TDI and TDO.

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

JTAG Port Recommended Operating Conditions and DC Characteristics

Parameter

Symbol

V_ILJ

Min.

–0.3

Max.

Unit Notes

0.3 * V_DD

V_DD+0.3

Test Port Input Low Voltage

V_IHJ

0.7 * V_DD

Test Port Input High Voltage

I_INHJ

TMS, TCK and TDI Input Leakage Current

TDO Output Leakage Current

Test Port Output High Voltage

Test Port Output Low Voltage

Test Port Output CMOS High

Test Port Output CMOS Low

–300

–1

100

I_INLJ

I_OLJ

–1

V_OHJ

V_OLJ

V_OHJC

V_OLJC

V_DD– 0.2

—

0.2

—

0.1

5, 6

5, 7

5, 8

5, 9

—

V_DD– 0.1

—

Notes:

1. Input Under/overshoot voltage must be –1 V < Vi < V

+1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.

DDn

≤ V ≤ V

ILJ

DDn

3. 0 V ≤ V ≤ V

ILJn

4. Output Disable, V

= 0 to V

DDn

OUT

5. The TDO output driver is served by the V supply.

= –2 mA

OHJ

= + 2 mA

OLJ

= –100 uA

= +100 uA

OHJC

OLJC

Rev: 1.03a 11/2011

22/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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