GS81302T06/11E-500/450/400/350
16M x 8 SigmaDDR-II+ SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
B
CQ
SA
SA
R/W
NW1
K
SA
LD
SA
SA
CQ
NC/SA
(288Mb)
NC
NC
NC
SA
K
NW0
SA
SA
NC
NC
DQ3
C
D
E
F
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
NC
V
V
SA
SA
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ2
NC
NC
ZQ
SS
SS
SS
SS
V
V
V
V
V
V
SS
SS
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
DD
DQ4
NC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
G
H
J
DQ5
V
V
V
V
V
V
V
REF
REF
DDQ
DDQ
NC
NC
NC
NC
NC
NC
DQ7
SA
NC
DQ1
NC
NC
DQ0
NC
NC
NC
TDI
K
L
NC
DQ6
NC
V
NC
NC
NC
NC
NC
SA
NC
NC
V
V
V
V
V
DDQ
SS
SS
SS
SS
M
N
P
R
V
V
NC
SS
SS
SS
SS
NC
V
SA
SA
SA
SA
SA
SA
SA
V
NC
NC
SA
SA
QVLD
ODT
SA
SA
NC
TCK
TMS
2
11 x 15 Bump BGA—15 x 17 mm Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7.
2. Pin B5 is the expansion address.
Rev: 1.04 8/2021
3/26
© 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.