Datasheet > GS81302T11E-400I

GS81302T11E-400I

更新时间： 2023-12-06 20:13:34

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GS81302T11E-400I 数据手册

GS81302T06/11E-500/450/400/350

Common I/O SigmaDDR-II+ Burst of 2 SRAM Truth Table

R/W

Operation

A + 0

Hi-Z / *

A + 1



Hi-Z / *

D@K_n+1

Q@K_n+3

Deselect

Write

D@K_n+1

Q@K_n+2



Read

Notes:

1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”.

2. D1 and D2 indicate the first and second pieces of Write Data transferred during Write operations.

3. Q1 and Q2 indicate the first and second pieces of Read Data transferred during Read operations.

4. When On-Die Termination is disabled (ODT = 0), DQ drivers are disabled (i.e., DQ pins are tri-stated) for one cycle in response to NOP

and Write commands, 2.5 cycles after the command is sampled.

5. When On-Die Termination is enabled (ODT = 1), DQ drivers are disabled for one cycle in response to NOP and Write commands, 2.5

cycles after the command is sampled. The state of the DQ pins during that time (denoted by “*” in the table above) is determined by the

state of the DQ input termination. See the Input Termination Impedance Control section for more information.

Rev: 1.04 8/2021

7/26

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1...4 5 678 9 10...26

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型号	品牌	描述	获取价格	数据表
GS81302T11E-450	GSI	165 BGA	获取价格
GS81302T11E-450I	GSI	165 BGA	获取价格
GS81302T11E-500	GSI	165 BGA	获取价格
GS81302T11E-500I	GSI	165 BGA	获取价格
GS81302T11GE-300I	GSI	DDR SRAM, 16MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	获取价格
GS81302T11GE-333IT	GSI	DDR SRAM, 16MX9, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165	获取价格