Datasheet > GS81280Z18GT-400I

GS81280Z18GT-400I

更新时间： 2022-02-26 09:11:56

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
23页	369K
描述
144Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS81280Z18GT-400I 数据手册

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GS81280Z18/36GT-400/333/250/200

Synchronous Truth Table

State

Diagram

Key

Address

Used

Operation

ADSP

ADSC

ADV

Deselect Cycle, Power Down

Read Cycle, Begin Burst

Write Cycle, Begin Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

Notes:

None

High-Z

None

High-Z

None

High-Z

None

High-Z

External

Current

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E²= 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

Rev: 1.01 5/2017

7/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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