Datasheet > GS81280Z18GT-250IV

GS81280Z18GT-250IV

更新时间： 2022-02-26 09:36:45

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
22页	367K
描述
144Mb Pipelined and Flow Through Synchronous NBT SRAM

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GS81280Z18GT-250IV 数据手册

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GS81280Z18/36GT-xxxV

TQFP Pin Descriptions

Symbol

A0, A1

Type

Description

Burst Address Inputs; Preload the burst counter

Address Inputs

Clock Input Signal

Byte Write signal for data inputs DQA1-DQA9; active low

Byte Write signal for data inputs DQB1-DQB9; active low

Byte Write signal for data inputs DQC1-DQC9; active low

Byte Write signal for data inputs DQD1-DQD9; active low

Write Enable; active low

Chip Enable; active low

E²

Chip Enable; Active High. For self decoded depth expansion

Chip Enable; Active Low. For self decoded depth expansion

Output Enable; active low

ADV

CKE

DQ^A

DQ^B

DQ^C

DQ^D

Advance/Load; Burst address counter control pin

Clock Input Buffer Enable; active low

Byte A Data Input and Output pins

I/O

Byte B Data Input and Output pins

Byte C Data Input and Output pins

Byte D Data Input and Output pins

Power down control; active high

Pipeline/Flow Through Mode Control; active low

Linear Burst Order; active low

LBO

Core power supply

Ground

Output driver power supply

No Connect

DDQ

—

Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may

—

be left unconnected, tied Low (to V ), or tied High (to V

or V ).

DDQ

Rev: 1.01 5/2017

4/21

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1 2 345 6 7...22

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