Datasheet > GS81280E36GT-333I

GS81280E36GT-333I

更新时间： 2023-12-06 20:13:33

品牌	Logo	应用领域
GSI		/
页数	文件大小	规格书
22页	421K
描述
100 TQFP

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GS81280E36GT-333I 数据手册

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GS81280E18/32/36GT-400/333/250/200

Mode Pin Functions

Mode Name

Pin Name

State

Function

Linear Burst

Interleaved Burst

Flow Through

Pipeline

Burst Order Control

Output Register Control

Power Down Control

LBO

H or NC

L or NC

Active

Standby, I_DD= I_SB

Note:

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in

the default states as specified in the above tables.

Burst Counter Sequences

Linear Burst Sequence

Interleaved Burst Sequence

A[1:0]

1st address

2nd address

3rd address

4th address

1st address

2nd address

3rd address

4th address

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

Rev: 1.01a 8/2017

7/22

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1...4 5 678 9 10...22

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