Datasheet > GM71CS17400CJ-7

GM71CS17400CJ-7

更新时间： 2024-01-28 03:33:50

品牌	Logo	应用领域
海力士 - HYNIX		动态存储器
页数	文件大小	规格书
10页	97K
描述
DRAM

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技术参数
数据手册

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GM71CS17400CJ-7 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

GM71CS17400CJ-7 数据手册

GM71C(S)17400C/CL

Capacitance (VCC = 5.0V+/-10%, TA = 25C)

Symbol

CI1

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

Min

Max

Unit

Note

CI2

CI/O

1, 2

Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

2. CAS = VIH to disable DOUT

AC Characteristics (VCC = 5.0V+/-10%, Vss=0V, TA = 0 ~ 70C, Notes 1, 2, 18,19)

Test Conditions

Input rise and fall times : 5ns

Input timing reference levels : 0.8V, 2.4V

Output timing reference levels : 0.4V, 2.4V

Output load : 2 TTL gate + C (100pF)

(Including scope and jig)

Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)

GM71C(S)17400 GM71C(S)17400 GM71C(S)17400

C/CL-5

C/CL-6

C/CL-7

Unit Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

RAS Precharge Time

110

130

tRP

CAS Precharge Time

RAS

CAS

ASR

RAH

ASC

CAH

RCD

RAD

RSH

CSH

CRP

ODD

DZO

DZC

RAS Pulse Width

50 10,000

10,000

CAS Pulse Width

13 10,000 15 10,000 18 10,000 ns

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

45 20

30 15

CAS Hold Time

CAS to RAS Precharge Time

OE to DIN Delay Time

OE Delay Time from DIN

CAS Delay Time from DIN

Transition Time (Rise and Fall)

Rev 0.1 / Apr’01

1 2 345 6 7...10

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