Datasheet > GM71C18160C(CL)

GM71C18160C(CL)

更新时间： 2022-01-19 14:17:00

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
10页	112K
描述
1Mx16\|5V\|1K\|5/6\|FP/EDO DRAM - 16M

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GM71C18160C(CL) 数据手册

GM71C18160C

GM71CS18160CL

Capacitance (VCC = 5V+/-10%, TA = 25C)

Symbol

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

M in

Max

Unit

Note

I/O

1, 2

Note: 1. Capacitance measured with B oonton Meter or effective capacitance measuring method.

2. UCAS and LCAS = VIH to disable DOUT

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Note 1, 2, 18)

Test Conditions

Input rise and fall times : 5 ns

Output timing reference levels : 0.4V, 2.4V

Output load : 2TTL gate + CL (100 pF)

(Including scope and jig)

Input timing reference levels : 0.8V , 2.4V

R ead, W r ite, Read-Modify-W r ite and Refr esh Cycles (Common Parameters)

GM71C(S)18160 GM71C(S)18160 GM71C(S)18160

C/CL-5

C/CL-6

C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

R A S Precharge Time

110

130

R C

tRP

CAS Precharge Time

tR A S

RAS Pulse Width

50 10,000

13 10,000

10,000

tCAS

CAS Pulse Width

15 10,000

18 10,000

tA S R

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

tRAH

tASC

tCAH

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

tRCD

tR A D

tRSH

CAS Hold Time

tCSH

CAS to RAS Precharge Time

OE to DIN Delay Time

tCRP

tODD

tDZO

OE Delay Time from DIN

CAS Delay Time from DIN

T ransition Time (Rise and Fall)

tDZC

Rev 0.1 / Apr’01

1 2 3 456 7 8...10

下载PDF

与GM71C18160C(CL)相关器件

型号	品牌	描述	获取价格	数据表
GM71C18160CJ-5	ETC	x16 Fast Page Mode DRAM	获取价格
GM71C18160CJ-6	ETC	x16 Fast Page Mode DRAM	获取价格
GM71C18160CJ-7	ETC	x16 Fast Page Mode DRAM	获取价格
GM71C18160CT-5	ETC	x16 Fast Page Mode DRAM	获取价格
GM71C18160CT-6	ETC	x16 Fast Page Mode DRAM	获取价格
GM71C18160CT-7	ETC	x16 Fast Page Mode DRAM	获取价格