Datasheet > GDQ2A8AA-CE

GDQ2A8AA-CE

更新时间： 2023-12-06 20:00:57

品牌	Logo	应用领域
兆易创新 - GIGADEVICE		电子通信驱动动态存储器双倍数据速率
页数	文件大小	规格书
100页	2670K
描述
近年来，随着生活娱乐、车载影音、网络通信、智慧家庭等各种消费类电子应用的蓬勃发展，利基型DDR4接口的DRAM需求迅猛上升，未来更多新兴应用和产品的诞生，将进一步驱动市场对利基型DDR4的需求。兆

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GDQ2A8AA-CE 数据手册

DDR4 SDRAM

1 FEATURES

GDQ2A8AA

◆ Power supply: V_DD= V_DDQ= 1.2V (1.14V to 1.26V); V_PP= 2.5V (2.375V to 2.75V)

◆ JEDEC standard package: 78-Ball FBGA (x8)

◆ Array Configuration: 16 Banks (x8) 4 groups of 4 banks

◆ 8n-Bit prefetch architecture

◆ Burst Length (BL): 8 and 4 with Burst Chop (BC)

◆ Programmable CAS Latency (CL)

◆ Programmable CAS Write Latency (CWL)

◆ Internal generated V_REFfor data inputs

◆ Data Mask (DM) for write data

◆ On-Die Termination (ODT): Support Nominal, Park and Dynamic ODT

◆ Burst Length (BL): 8 and 4 with Burst Chop (BC)

◆ Interface: 1.2V Pseudo Open Drain (POD) IO

◆ Differential clock and data strobe inputs (CK_t ,CK_c; DQS_t, DQS_c)

◆ Per DRAM Addressability (PDA)

◆ Data Bus Inversion (DBI)

◆ Asynchronous reset for power up

◆ Maximum Power Saving Mode (MPSM)

◆ Precharge: Auto precharge option for each burst access

◆ Operating case temperature: -40°C ≤ T_CASE≤ 95°C

◆ Support auto-refresh and self-refresh mode

◆ Average Refresh Period:

-7.8μs at -40°C ≤ T_CASE≤ 85°C

-3.9μs at 85°C < T_CASE≤ 95°C

◆ Fine granularity refresh 2x, 4x mode for smaller t_RFC

◆ Programmable data strobe preambles

◆ Command Address (CA) Parity is supported

◆ Write Cyclic Redundancy Code (CRC) is supported

◆ Connectivity test mode (TEN) is supported

◆ Gear Down Mode

◆ Output driver calibration through ZQ pin (R_ZQ: 240ohm ± 1%)

◆ JEDEC JESD-79-4D compliant

◆ RoHS compliant

Note:

1. The functionality described and the timing specifications included in this datasheet are for the DLL Enabled mode of

operation (normal operation), unless specifically stated otherwise.

DS-00855-GDQ2A8AA-Rev1.4

2023/6/25

1 2 3 456 7 8...100

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