DDR4 SDRAM
GDQ2A8AA
Contents
1
2
FEATURES ...........................................................................................................................................................5
1.1
1.2
Speed Bins ....................................................................................................................................................6
Address Table................................................................................................................................................6
ORDERING INFORMATION.................................................................................................................................7
2.1
2.2
Part Number Decoding..................................................................................................................................7
Valid Part Numbers .......................................................................................................................................8
3
4
PACKAGE INFORMATION ..................................................................................................................................9
3.1
Package 78-Ball FBGA (x8) ..........................................................................................................................9
BALL ASSIGNMENTS .......................................................................................................................................10
4.1
4.2
78-Ball FBGA (x8) Ball Assignments...........................................................................................................10
Ball Description............................................................................................................................................11
5
6
FUNCTIONAL BLOCK DIAGRAM.....................................................................................................................14
ABSOLUTE MAXIMUM RATINGS.....................................................................................................................15
6.1
Absolute Maximum DC Ratings...................................................................................................................15
Recommended Supply Operating Conditions .............................................................................................15
DRAM Component Operating Temperature Range ....................................................................................15
6.2
6.3
7
AC AND DC INPUT MEASUREMENT LEVELS................................................................................................17
7.1
AC and DC Logic Input Levels for Single-ended Signals............................................................................17
AC and DC Logic Input Measurement Levels: VREF Tolerances .................................................................18
AC and DC Logic Input Levels for Differential Signals................................................................................18
7.2
7.3
7.3.1 AC and DC Logic Input Levels for Differential Signals ............................................................................18
7.3.2 Differential Swing Requirements for Clock (CK_t - CK_c) ......................................................................19
7.3.3 Differential Swing Requirements for Clock (CK_t - CK_c) ......................................................................20
7.3.4 Address, Command, and Control Overshoot/Undershoot Specifications ...............................................21
7.3.5 Clock Overshoot/Undershoot Specifications ...........................................................................................22
7.3.6 Data, Strobe and Mask Overshoot/Undershoot Specifications ...............................................................23
7.4
Slew Rate Definitions for Differential Input Signals.....................................................................................24
7.4.1 Slew Rate Definitions for Differential Input Signals .................................................................................24
7.4.2 Slew Rate Definitions for Single-ended Input Signals (CMD/ADD).........................................................24
7.5
CK Differential Input Cross Point Voltage ...................................................................................................25
CMOS Rail to Rail Input Levels for RESET_n.............................................................................................26
AC and DC Logic Input Levels for DQS Signals .........................................................................................27
7.6
7.7
7.7.1 Differential Signal Definition.....................................................................................................................27
7.7.2 Differential Swing Requirements for DQS (DQS_t - DQS_c)..................................................................27
7.7.3 Peak Voltage Calculation Method............................................................................................................28
DS-00855-GDQ2A8AA-Rev1.4
2
2023/6/25
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