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GAL26CLV12D-5LJ PDF预览

GAL26CLV12D-5LJ

更新时间: 2024-09-20 22:08:55
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莱迪思 - LATTICE /
页数 文件大小 规格书
13页 225K
描述
Low Voltage E2CMOS PLD Generic Array Logic

GAL26CLV12D-5LJ 数据手册

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GAL26CLV12  
Low Voltage E2CMOS PLD  
Generic Array Logic™  
FEATURES  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 5 ns Maximum Propagation Delay  
— Fmax = 200 MHz  
I/CLK  
INPUT  
I/O/Q  
RESET  
8
— 3.5 ns Maximum from Clock Input to Data Output  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
— UltraMOS® Advanced CMOS Technology  
I
I
I
I
I
I
I
I
I
I
I
I
8
8
• 3.3V LOW VOLTAGE 26CV12 ARCHITECTURE  
— JEDEC-Compatible 3.3V Interface Standard  
— Inputs and I/O Interface with Standard 5V TTL Devices  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
8
10  
12  
12  
10  
8
• TWELVE OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— Glue Logic for 3.3V Systems  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
8
8
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
8
PRESET  
Description  
Pin Configuration  
The GAL26CLV12D, at 5 ns maximum propagation delay time,  
provides higher performance than its 5V counterpart. The  
GAL26CLV12D can interface with both 3.3V and 5V signal levels.  
The GAL26CLV12D is manufactured using Lattice Semiconductor's  
advanced 3.3V E2CMOS process, which combines CMOS with  
Electrically Erasable (E2) floating gate technology. High speed erase  
times (<100ms) allow the devices to be reprogrammed quickly and  
efficiently.  
PLCC  
4
2
28  
26  
25  
5
7
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
GND  
I/O/Q  
I/O/Q  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user.  
I
VCC  
23  
GAL26CLV12D  
Top View  
I
I
I
I
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
9
21  
19  
11  
12  
14  
16  
18  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
July 1997  
26clv12_02  
1

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