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FWLF16217DXX PDF预览

FWLF16217DXX

更新时间: 2022-02-26 12:44:55
品牌 Logo 应用领域
菲尼萨 - FINISAR /
页数 文件大小 规格书
11页 5799K
描述
Multi-rate CWDM Pluggable SFP Transceiver

FWLF16217DXX 数据手册

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FWLF16217Dxx SFP Product Specification – May 2010  
I.  
Pin Descriptions  
Pin  
1
2
3
4
5
6
7
8
Symbol  
Name/Description  
Transmitter Ground (Common with Receiver Ground)  
Transmitter Fault. Not supported.  
Ref.  
1
VEET  
TFAULT  
TDIS  
Transmitter Disable. Laser output disabled on high or open.  
2
3
3
3
4
5
1
1
1
MOD_DEF(2) Module Definition 2. Data line for Serial ID.  
MOD_DEF(1) Module Definition 1. Clock line for Serial ID.  
MOD_DEF(0) Module Definition 0. Grounded within the module.  
Rate Select  
LOS  
No connection required  
Loss of Signal indication. Logic 0 indicates normal operation.  
Receiver Ground (Common with Transmitter Ground)  
Receiver Ground (Common with Transmitter Ground)  
Receiver Ground (Common with Transmitter Ground)  
Receiver Inverted DATA out. AC Coupled  
Receiver Non-inverted DATA out. AC Coupled  
Receiver Ground (Common with Transmitter Ground)  
Receiver Power Supply  
9
VEER  
VEER  
VEER  
RD-  
RD+  
VEER  
VCCR  
VCCT  
VEET  
10  
11  
12  
13  
14  
15  
16  
17  
18  
1
1
Transmitter Power Supply  
Transmitter Ground (Common with Receiver Ground)  
Transmitter Non-Inverted DATA in. 100 ohm termination between TD+  
and TD-, AC Coupled thereafter.  
TD+  
19  
20  
TD-  
VEET  
Transmitter Inverted DATA in. See TD+  
Transmitter Ground (Common with Receiver Ground)  
1
Notes:  
1. Circuit ground is internally isolated from chassis ground.  
2. Laser output disabled on TDIS >2.0V or open, enabled on TDIS <0.8V.  
3. Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V and 5.5V.  
MOD_DEF(0) pulls line low to indicate module is plugged in.  
4. Finisar 2x receiver achieves simultaneous 1x and 2x operation without active control.  
5. LOS is open collector output. Should be pulled up with 4.7k – 10kohms on host board to a voltage  
between 2.0V and 5.5V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.  
VeeT  
TD-  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VeeT  
1
2
TXFault  
TD+  
3
TX Disable  
MOD-DEF(2)  
MOD-DEF(1)  
MOD-DEF(0)  
Rate Select  
LOS  
VeeT  
VccT  
VccR  
VeeR  
RD+  
RD-  
4
5
Towards  
Bezel  
Towards  
ASIC  
6
7
8
9
VeeR  
VeeR  
VeeR  
10  
Diagram of Host Board Connector Block Pin Numbers and Names  
Ó Finisar Corporation May 2010 Rev. A  
Page 2  

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