Datasheet > FS6370-01-XTD

FS6370-01-XTD

更新时间： 2024-02-01 10:19:29

品牌	Logo	应用领域
AMI		光电二极管
页数	文件大小	规格书
24页	328K
描述
Clock Generator, CMOS, PDSO16,

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技术参数
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FS6370-01-XTD 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	unknown	风险等级：	5.82
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3.3/5 V	认证状态：	Not Qualified
子类别：	Clock Generators	最大压摆率：	43 mA
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

FS6370-01-XTD 数据手册

Data Sheet

FS6370-01/FS6370-01g EEPROM Programmable 3-PLL Clock Generator IC

6.1.1 Write Operation

The EEPROM can only be written to with the random register write procedure (see Section 8.2.2). The procedure consists of the device address, the

Following the STOP condition, the EEPROM initiates its internally timed 4ms write cycle, and commits the data byte to memory. No acknowledge signals

are generated during the EEPROM internal write cycle.

If a stop bit is transmitted before the entire write command sequence is complete, then the command is aborted and no data is written to memory.

If more than eight bits are transmitted before the stop bit is sent, then the EEPROM will clear the previously loaded data byte and will begin loading the

data buffer again.

6.1.2 Acknowledge Polling

The EEPROM does not acknowledge while it internally commits data to memory. This feature can be used to increase data throughput by determining

when the internal write cycle is complete.

The process is to initiate the random register write procedure with a START condition, the EEPROM device address, and the write command bit (R/W=0).

If the EEPROM has completed its internal 4ms write cycle, the EEPROM will acknowledge on the next clock, and the write command can continue.

If the EEPROM has not completed the internal 4ms write cycle, the random register write procedure must be restarted by sending the START condition,

device address and R/W bit. This sequence must be repeated until the EEPROM acknowledges.

6.1.3 Read Operation

The EEPROM supports both the random register read procedure and the sequential register read procedure (both are outlined in Section 6).

For sequential read operations, the EEPROM has an internal address pointer that increments by one at the end of each read operation. The pointer directs

the EEPROM to transmit the next sequentially addressed data byte, allowing the entire memory contents to be read in one operation.

6.2 Direct Register Programming

The FS6370 control registers may be directly accessed by simply using the FS6370 device address in the read or write operations. The operation of the

device will follow the register values. The register map of the FS6370 is identical to that of the EEPROM shown in Table 3.

The FS6370 supports the random read and write procedures, as well as the sequential read and write procedures described in Section 8.

The device address for the FS6370 is:

7.0 Cost Reduction Migration Path

The FS6370 is compatible with the programmable register-based FS6377 or a fixed-frequency ROM-based clock generator. Attention should be paid to

the board layout if a migration path to either of these devices is desired.

7.1 Programming Migration Path

If the design can support I²C programming overhead, a cost reduction from the EEPROM-based FS6370 to the register-based FS6377 is possible.

Figure 5 shows the five pins that may not be compatible between the various devices if programming of the FS6370 or the FS6377 is desired.

AMI Semiconductor - Rev. 2.0, Mar. 05

www.amis.com.

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与FS6370-01-XTD相关器件

型号	品牌	描述	获取价格	数据表
FS6370-01-XTP	AMI	Clock Generator, CMOS, PDSO16,	获取价格
FS6377	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01	AMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G	AMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G-XTD	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格
FS6377-01G-XTP	ONSEMI	Programmable 3-PLL Clock Generator IC	获取价格

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