Datasheet > FPD87392BXBVQ

FPD87392BXBVQ

更新时间： 2024-01-29 23:26:26

品牌	Logo	应用领域
美国国家半导体 - NSC		显示器电脑控制器
页数	文件大小	规格书
30页	1976K
描述
+3.3V TFT-LCD Timing Controller with Dual LVDS Inputs/Dual RSDS⑩ Outputs for TFT-LCD Monitor and Notebook (SXGA/SXGA+/UXGA)

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FPD87392BXBVQ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	风险等级：	5.92
JESD-609代码：	e0	端子面层：	Tin/Lead (Sn85Pb15)
Base Number Matches：	1

FPD87392BXBVQ 数据手册

July 2004

FPD87392BXB

+3.3V TFT-LCD Timing Controller with Dual LVDS

™

Inputs/Dual RSDS Outputs for TFT-LCD Monitor and

Notebook (SXGA/SXGA+/UXGA)

General Description

Features

n Input frequency range from 25 MHz to 85 MHz

n Support display resolutions SXGA (1280x1024), SXGA+

(1400x1050) and UXGA (1600x1200)

The FPD87392BXB Panel Timing Controller is an integrated

™

FPD-Link + RSDS + TFT-LCD Timing Controller. The logic

architecture is implemented using standard and default tim-

ing controller functionality based on an Embedded Gate

Array. The device is reconfigurable to the needs of a specific

application by providing user-defined specifications or cus-

tomer supplied VHDL/Verilog code.

n Embedded gate array for custom panel timing

™

n RSDS (Reduced Swing Differential Signaling) Column

Driver bus for low power and reduced EMI

n Drives RSDS column driver up to 170 Mb/s with an 85

™

The FPD87392BXB is a timing controller that combines an

LVDS dual pixel input interface with National’s Reduced

MHz clock

n 6 or 8 bit LVDS dual pixel input interface (FPD-Link)

n Virtual 8-bit color depth in FRC mode

n Flexible RSDS data output mapping for Bottom or Top

™

Swing Differential Signaling (RSDS ) output column driver

interface for SXGA, SXGA+ and UXGA resolutions. It re-

sides on the TFT-LCD panel and provides the data buffering

™

mount

™

and control signal generation. The RSDS data path to the

n Supports 1 and 2 line inversion mode for RVS output

n Supports Graphics Controllers with spread spectrum

interface for lower EMI

column driver contributes toward lowering radiated EMI and

™

reduced system dynamic power consumption. The RSDS

dual 12 pair differential bus conveys up to 24-bit color data

for SXGA/SXGA+/UXGA panels when using VESA 60Hz

standard timing.

n Free Run Mode Function

n Fail-safe function in DE mode (Bonding Option)

n Supports DE mode and SYNC only mode (Bonding

Option)

n Power-On-Reset Support

n CMOS circuitry operates from a 3.0V to 3.6V supply

n 128 TQFP package with body size 14mm x 14mm x

1.0mm, 0.4mm Pitch

DS201043

www.national.com

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