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FMS6408

更新时间： 2022-12-12 00:10:49
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飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
9页 248K
描述
Triple Video Filter Driver for RGB and YUV Signals

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FMS6408 数据手册

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FMS6408  
DATA SHEET  
Pin Configuration  
Pin#  
Pin  
Type Description  
Y
V
Y
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
INA  
INA  
INA  
CC  
1
Y
Input Y (Luminance) or Green input A, must be  
connected to a signal which includes sync  
INA  
U
V
OUT  
FMS6408  
14-pin  
TSSOP  
2
3
4
5
U
V
Input U or Blue input A  
INA  
BYPASS  
Input V or Red input A  
INA  
U
GND  
OUT  
GND  
Input Must be tied to ground, do not float  
Y
GND  
INB  
Y
Input Y (Luminance) or Green input B, must be  
connected to a signal which includes sync  
INB  
U
V
INB  
OUT  
6
7
8
U
V
Input U or Blue input B  
Input V or Red input B  
INB  
V
IN  
(A/B)  
MUX  
8
INB  
INB  
IN  
(A/B) Input Mux select, A = ‘1’, B = ‘0’, must be  
externally tied high or low  
MUX  
9
V
Output V or Red output  
OUT  
10  
11  
12  
GND  
Input Must to be tied to ground, do not float  
Output U or Blue output  
U
OUT  
BYPASS  
(Bypass/Filter)  
Input Filter bypass, BYPASS = ‘1’, FILTER = ‘0’,  
must be externally tied high or low  
13  
14  
Y
Output Y or Green output  
Input +5V supply  
OUT  
V
CC  
Sync processing is based on the Y/G input channel in all  
operating modes.  
Functional Description  
Introduction  
This product is a three channel monolithic continuous time  
video filter designed for reconstructing YUV, YC CV or  
RGB signals from a video D/A source. Inputs should be AC  
coupled while outputs can be either AC or DC coupled.  
The reconstruction filters approximate a 5th order Butter-  
worth response optimized for minimum overshoot and flat  
group delay. This provides a maximally flat response in  
terms of delay and amplitude. Each of the three outputs is  
capable of driving 2Vpp into 75Ω loads.  
Inputs  
The inputs will typically be driven by either a low impedance  
source of 1Vpp or the output of a 75Ω terminated line driven  
by the output of a current DAC. In either case, the inputs  
must be capacitively coupled to allow the sync-detect and  
DC restore circuitry to operate properly.  
Outputs  
The outputs are low impedance voltage drivers which can  
handle either a single or dual load. A single load consists of  
a 75Ω series termination resistor feeding a 75Ω terminated  
line for a total load at the part of 150Ω. Even when two loads  
are present (75Ω) the driver will produce a full 2Vpp signal  
at its output pin. The driver can also be used to drive an AC  
coupled single or dual load. When driving a dual load either  
output will still function if the other output connection is  
inadvertently shorted providing these loads are AC coupled.  
All channels are clamped during the sync interval to set the  
appropriate dc output level. Sync tip clamping greatly reduces  
the effective input time constant allowing the use of small  
low cost input coupling capacitors. The input will settle to  
10mV in 2ms for typical DC shifts present in the video signal.  
In most applications the input coupling capacitors are 0.1µF.  
The inputs typically sink 1uA of current during active video.  
For YUV signals, this translates into a 2mV tilt in a horizon-  
tal line at the Y output. During sync, the clamp restores this  
leakage current by sourcing an average of 20µA over the  
clamp interval. Any change in the coupling capacitor values  
will affect the amount of tilt per line. Any reduction in tilt  
will come with an increase in settling time.  
REV. 2C August 31, 2004  
5
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