The same method can be used for biased signals with the addi-
tion of a pull-up resistor to make sure the clamp never operates.
The internal pull-down resistance is 800kΩ 20% so the exter-
nal resistance should be 7.5MΩ to set the DC level to 500mV. If
a pull-up resistance less than 7.5MΩ is desired, an external
pull-down can be added such that the DC input level is set to
500mV.
Power Dissipation
The FMS6246 output drive configuration must be considered
when calculating overall power dissipation. Care must be taken
not to exceed the maximum die junction temperature. The fol-
lowing example can be used to calculate the FMS6246’s power
dissipation and internal temperature rise.
Tj = TA + Pd • ΘJA
where Pd = PCH1 + PCH2 + PCHx
and PCHx = Vs • ICH - (VO2/RL)
where
External Video
source must
be AC-coupled.
0.1u
75
LCVF
Bias
Input
7.5M
VO = 2Vin + 0.280V
ICH = (ICC / 6) + (VO/RL)
Vin = RMS value of input signal
ICC = 60mA
500mV +/-350mV
75
Figure 6. Biased SCART with DC-coupled Outputs
Vs = 5V
The same circuits can be used with AC-coupled outputs if
desired.
RL = channel load resistance
Board layout can also affect thermal characteristics. Refer to the
Layout Considerations Section for more information.
0V - 1.4V
75
220u
DVD or
STB
SoC
LCVF
Clamp
Inactive
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance and thermal characteristics. Fairchild
offers a demonstration board, FMS6246DEMO, to use as a
guide for layout and to aid in device testing and characterization.
The FMS6246DEMO is a 4-layer board with a full power and
ground plane. Following this layout configuration will provide the
optimum performance and thermal characteristics. For optimum
results, follow the steps below as a basis for high frequency lay-
out:
DAC
Output
Figure 7. DC-coupled inputs, AC-coupled Outputs
0V - 1.4V
•
•
•
•
Include 10µF and 0.1µF ceramic bypass capacitors
0.1u
75
220u
DVD or
STB
SoC
DAC
Output
LCVF
Clamp
Active
Place the 10µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
For multi-layer boards, use a large ground plane to help dissi-
pate heat
•
•
For 2 layer boards, use a ground plane that extends beyond
the device by at least 0.5”
Figure 8. AC-coupled inputs and outputs
Minimize all trace lengths to reduce series inductances
External video
source must
be AC-coupled.
0.1u
75
220u
LCVF
Clamp
Active
7.5M
500mV +/-350mV
75
Figure 9. Biased SCART with AC-Coupled Outputs
NOTE: The video tilt or line time distortion will be dominated by
the AC-coupling capacitor. The value may need to be increased
beyond 220uF in order to obtain satisfactory operation in some
applications.
6
www.fairchildsemi.com
FMS6246 Rev. 1A