FM25W256

更新时间： 2024-02-26 14:14:24

品牌	Logo	应用领域
铁电 - RAMTRON		/
页数	文件大小	规格书
13页	293K
描述
256Kb Wide Voltage SPI F-RAM

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中文翻译

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技术参数
数据手册

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FM25W256 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP8,.25	Reach Compliance Code：	unknown
风险等级：	5.88	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
内存密度：	262144 bit	内存集成电路类型：	NON-VOLATILE SRAM
内存宽度：	8	端子数量：	8
字数：	32768 words	字数代码：	32000
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	32KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3/5 V	认证状态：	Not Qualified
最大待机电流：	0.00015 A	子类别：	SRAMs
最大压摆率：	0.007 mA	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
Base Number Matches：	1

FM25W256 数据手册

FM25W256 - 256Kb SPI F-RAM

by terminating a write cycle (/CS high) or by using

the WRDI command.

The WPEN bit controls the effect of the hardware

/WP pin. When WPEN is low, the /WP pin is

ignored. When WPEN is high, the /WP pin controls

write access to the status register. Thus the Status

BP1 and BP0 are memory block write protection bits.

They specify portions of memory that are write

protected as shown in the following table.

This scheme provides a write protection mechanism,

which can prevent software from writing the

memory under any circumstances. This occurs if the

BP1 and BP0 are set to 1, the WPEN bit is set to 1,

and /WP is set to 0. This occurs because the block

protect bits prevent writing memory and the /WP

signal in hardware prevents altering the block

protect bits (if WPEN is high). Therefore in this

condition, hardware must be involved in allowing a

write operation. The following table summarizes the

write protection conditions.

Table 3. Block Memory Write Protection

BP1

BP0 Protected Address Range

None

6000h to 7FFFh (upper ¼)

4000h to 7FFFh (upper ½)

0000h to 7FFFh (all)

The BP1 and BP0 bits and the Write Enable Latch

are the only mechanisms that protect the memory

from writes. The remaining write protection features

protect inadvertent changes to the block protect bits.

Table 4. Write Protection

WEL

WPEN

/WP

Protected Blocks

Protected

Unprotected Blocks

Protected

Unprotected

Status Register

Protected

Unprotected

Protected

Unprotected

the middle of a write operation will have no effect

until the next falling edge of /CS.

Memory Operation

The SPI interface, which is capable of a relatively

high clock frequency, highlights the fast write

capability of the F-RAM technology. Unlike SPI-bus

EEPROMs, the FM25W256 can perform sequential

writes at bus speed. No page register is needed and

any number of sequential writes may be performed.

Read Operation

After the falling edge of /CS, the bus master can issue

a READ op-code. Following this instruction is a two-

byte address value. The upper bit of the address is a

don’t care. In total, 15-bits specify the address of the

first byte of the read operation. After the op-code and

address are complete, the SI line is ignored. The bus

master issues 8 clocks, with one bit read out for each.

Addresses are incremented internally as long as the

bus master continues to issue clocks. If the last

address of 7FFFh is reached, the counter will roll

over to 0000h. Data is read MSB first. The rising

edge of /CS terminates a READ op-code operation.

A read operation is shown in Figure 10.

Write Operation

All writes to the memory array begin with a WREN

op-code. The next op-code is the WRITE instruction.

This op-code is followed by a two-byte address

value. The upper bit of the address is a “don’t care”.

In total, 15-bits specify the address of the first data

byte of the write operation. Subsequent bytes are data

and they are written sequentially. Addresses are

incremented internally as long as the bus master

continues to issue clocks. If the last address of 7FFFh

is reached, the counter will roll over to 0000h. Data is

written MSB first. A write operation is shown in

Figure 9.

Hold

The /HOLD pin can be used to interrupt a serial

operation without aborting it. If the bus master pulls

the /HOLD pin low while SCK is low, the current

operation will pause. Taking the /HOLD pin high

while SCK is low will resume an operation. The

transitions of /HOLD must occur while SCK is low,

but the SCK and /CS pins can toggle during a hold

state.

Unlike EEPROMs, any number of bytes can be

written sequentially and each byte is written to

memory immediately after it is clocked in (after the

8^thclock). The rising edge of /CS terminates a

WRITE op-code operation. Asserting /WP active in

Rev. 1.3

Feb. 2011

Page 7 of 13

1...4 5 678 9 10...13

中文翻译

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与FM25W256相关器件

型号	品牌	获取价格	描述	数据表
FM25W256_13	CYPRESS	获取价格	256Kb Wide Voltage SPI F-RAM
FM25W256-G	CYPRESS	获取价格	256Kb Wide Voltage SPI F-RAM
FM25W256-G	RAMTRON	获取价格	256Kb Wide Voltage SPI F-RAM
FM25W256-G	INFINEON	获取价格	铁电存储器 (F-RAM)
FM25W256-GTR	RAMTRON	获取价格	256Kb Wide Voltage SPI F-RAM
FM25W256-GTR	CYPRESS	获取价格	256Kb Wide Voltage SPI F-RAM
FM25W256-GTR	INFINEON	获取价格	铁电存储器 (F-RAM)
FM25W256-S	ETC	获取价格	256Kb FRAM Wide Voltage Serial Memory
FM25W32	FM	获取价格	SPI NOR Flash
FM25W3P1-K120	MOLEX	获取价格	D Subminiature Connector, 25 Contact(s), Male, Solder Terminal,

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